AC37 High-Speed Communication Adapter Card
2-3
INTERRUPT ENABLE REGISTER:
OFFSET 1 - READ/WRITE
This register is used to enable or disable the various types of host CPU interrupts which can be generated by the
AC37. Disabling an interrupt prevents it from being indicated as active in the Interrupt Identification Register and
from activating the host CPU interrupt line. All other system functions operate in their normal manner, regardless
of their interrupt enable status. The Interrupt Enable Register is defined below:
Bit 0:
Received Data Available Interrupt Enable
When set to a logic 1, a received data available interrupt is generated whenever the
Receive Data Available bit is set in the Line Status Register. Refer to the description of
the Receive Data Available bit in the Line Status Register.
Bit 1:
Transmit Buffer Register Empty Interrupt Enable
When set to logic 1, a transmit buffer empty interrupt is generated whenever the
transmit FIFO is ready to accept data. Refer to the description of the Transmit Buffer
Empty flag (bit 5) in the Line Status Register.
Bit 2:
Receiver Line Status Interrupt Enable
When set to a logic 1, a receiver line status interrupt is generated upon a receive buffer
overrun error or a framing error. A receive buffer overrun error occurs when a data byte
is received while the receive FIFO is full. A framing error occurs if a stop bit was not
received at the appropriate time.
Bit 3:
Modem Status Interrupt Enable
When set to a logic 1, a modem status interrupt is generated when the IRQ line of the
Remote Bus is activated. Since the AC37 has no modem support, the Remote Bus IRQ
line is directed through what is normally the CTS status bit.
Bits 4–7:
Not Used
These bits are not used. They cannot be written to and will always read as zero.
REGISTER DEFINITION
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