AC37 High-Speed Communication Adapter Card
REGISTER DEFINITION
2-5
RESET CONTROL REGISTER:
OFFSET 2 - WRITE ONLY
This register is used to control the reset functions of the AC37. The bits of the Reset Control Register have the
following functions:
Bit 0:
Not Used
Bit 1:
Receive FIFO Reset
Writing a logic 1 to this bit will reset the receive FIFO. All data in the FIFO will be
cleared and it’s pointers reset to 0. Data being shifted into the receiver is not affected.
This bit is self clearing and it is not necessary to write a logic 0 afterward.
Bit 2:
Transmit FIFO Reset
Writing a logic 1 to this bit will reset the transmit FIFO. All data in the FIFO will be
cleared and it’s pointers reset to 0. Data being shifted out of the transmitter is not
affected. This bit is self clearing and it is not necessary to write a logic 0 afterward.
Bit 3:
Not Used
Bit 4:
CPU Reset
To reset the AC37 CPU, write a logic 1 to Bit 4 and verify the DLAB bit in the Line
Control is set to 1. This will have the same affect as cycling power to the AC37. Both
receive and transmit FIFOs are also reset. Baud Rate, Interrupt Control and Line Control
registers will be cleared and need reconfiguring by the host CPU. Since the reset cycle
can take two seconds, the host CPU should not try to reconfigure the AC37 registers
until 2 seconds after initiating a reset. This bit is self clearing and it is not necessary to
write a logic 0 afterward.
Bit 5:
Not Used
Bit 6:
Not Used
Bit 7:
Not Used
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