NCN51205GEVB
http://onsemi.com
6
Figure 5. VDD2 Undervoltage Threshold
t
V
DD2
V
DD2L
V
DD2H
<VDD2>
Comments:
<VDD2> is an internal signal which can be verified with the System State Service.
t
V
20V
V
20VL
V
20VH
<V20V>
Comments:
<V20V> is an internal signal which can be verified with the System State Service.
V
20V
_h
ys
t
Figure 6. V20V Undervoltage Threshold levels
Figure 7. SPI Bus Timing Diagram
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
DO
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
CLK
DI
CS
t
SCK
t
SDI_SET
t
SDI _HOLD
t
CS _SET
t
SCK _HIGH
t
SCK _LOW
t
CS_HOLD
t
CS _HIGH
t
SDO_VALID
