II.
C U R R E N T S T A B I L I Z I N G
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CV
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_ _ _
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T8
T 7 0
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T 71
s e r i e s
r eg ul ator
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P r i n c i p l e
d r aw i n g c u r r e n t s t a b i l i z i n g
F i g u r e
2 8
+out
- out
The output current flows through R70 . The voltage across R 70 is proportional
to the output current. Via P93 a reference voltage is added to the voltage
at the "+ out" side of R70 . At low output currents the potentional at the
wiper arm of P93 is more positive than the voltage at the T71e side
of
R70.
In this situation the "OR-gate" acts so, that the current limit does not effect
the "Series element" and the voltage stabilizer controls the output voltage.
If the output current through R70 increases , the voltage over R70 will
increase. If this voltage
=
reference voltage (wiper arm P93 ) , the output
current will not increase any more. This is because T5 starts conducting
which decreases the current through T4. The voltage at T4c then becomes
more positive. T6 acts as an emitter follower causing the voltage at T8b
to go positive. T8 being an PNP transistor conducts less, in turn reducing
the output current through the emitter follower T70. The maximum value
of this current is determined by P93 which is the " Current limit" control on
the front panel of the inst
rum
ent.
One resistor R70 is located in the emitter of each T71.
They act as current sharing resistors . The average voltage across the
R70 ' s is proportional to the output current. This average is taken by the
R 1 7 1 's , one to each resistor R70 .
The input of the " C C error amplifier" is protected by R2 1, R26, D3 and D4
(see circuit diagram) .
Under CC conditions the CV input of the "OR-gate" is not active, as the
bas e of T7 is reversed biased.
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