OKIFAX 610, Service Handbook, Page: 116 / 147

Table 8.1.1-4 External Bus Signal Timing Parameters
Interrupts hold tIH 0 - ns
BE setup tHS 15 - ns
BE hold tHH 0 - ns
REGDMA delay (CPU register
access) tRGD* - 30
tSL+10
ns
REGDMA delay (DMA access) tDMD* - 30
tSL+10
ns
/WAIT delay tWSD* - 30
tSL+12
ns
/RD,/WR delay tSD - 5 ns
/RD,/WR delay (Delay On=1) tSDD* - 30
tSL+10
ns
/RD,/WR delay(Delay On=2,3) tSDD - 12 ns
/WR delay (Early Off) tSDE* - 30
tSL+10
ns
Address delay tAD* - 30
tSL+10
ns
Chip Select delay tCSD* - 30
tSL+12
ns
Data setup (Read) tDS 12 - ns
Data hold (Read) tDHR 0 - ns
Data delay (Write) tDDW - 20 ns
Data delay(Internal access) tDDI - 30 ns
Data hold (Write, Internal
access) tDH tSL-10 - ns
Note : Valid value is whichever is the greater of the 2 values listed.
Test Conditions: 5.0V +5%/-10%, 70 , 50pF on all pins.
8.1.1.3 DRAM Controller
The DRAM chip provided is 1 Mega by 4 bits with maximum access time 100ns. Up to 1 column chip
selects, /CAS0, are supported to access total 1 Mega bytes. For basic memory of 1Mega bytes, 2
DRAM chips are provided, while for extended memory, 2 more chips are provided.
Address bus of DRAM are physically connected to address bit A0 to A9 of XFC. Row addresses are
gated onto the DRAM address bus first, followed by column addresses. The following operation
modes are supported: bytes access mode, early write mode and normal read mode. One wait state is
inserted in each DRAM bus cycle.
DRAM refresh is performed automatically, but only /CAS before /RAS operation is supported. Refresh
cycle time per 1024 cycles is 125ms. During power on when it is time to refresh DRAM and they are
not being accessed, the refresh cycle starts. When power down, no DRAM access occur, and DRAM
refresh continues on battery power.
8.1.1.4 CPU Interrupts
There are two ways to interrupt CPU, maskable interrupt (/MIRQ) and non-maskable interrupt NMI
(/DEBUG,/PWRDWN). Modem interrupt /MIRQ must hold active until the CPU processes the request.
The input /PWRDWN is OR'ed with the input /DEBUG and then
synchronized before NMI input. An active NMI signal branches program execution to the address
stored in NMI vector. When NMI represents power down, indicated by /PWRDWN low, the NMI
control firmware performs the necessary maintenance operation and then enable lockout register to
protect battery backed-up registers during power down.