Chapter 5 Notes on Debugging
Page 5-7
5.2 Other Notes
This Section covers other things to keep in mind when debugging user application programs
with the Oki ML670100 CPU Board.
5.2.1 System Reset Switch (RESET)
Do not press the system reset switch (RESET) on the Oki ML670100 CPU Board
during normal operation as it also resets the JTAG communications interface unit (Oki
Electric ADI Board or ARM Multi-ICE
TM
) joining the Board to the host computer and can
thus break the communications link to the ARM Software Development Toolkit running
on the development host.
5.2.2 User Cable
Do not crimp the user cable. Flexing it with excessive force can damage not only the
cable, but also the Oki ML670100 CPU Board itself.
5.2.3 External Clock
Do not change the OSCSEL switch to its external clock position unless the user
application system can provide an external clock signal matching the following
specifications.
Frequency:
See table below.
Duty:
50%
Level:
3.3 V DC
±
5%
Oki ML670100 CPU Board External Clock Specifications
FSEL pin input level
PLLEN pin input level
OSC0 pin input clock frequency
“H”
“H”
4 to 6 MHz
“L”
“H”
4 to 12 MHz
X
“L”
4 to 24 MHz
X: Don’t Care
Failure to match these specifications can lead to unpredictable CPU behavior and even
damage the Oki ML670100 CPU Board.
Summary of Contents for ML670100
Page 16: ...Chapter 1 Read Me First Page 1 12...
Page 79: ...Chapter 4 User Interface Page4 12...
Page 91: ...Chapter 5 Notes on Debugging Page 5 12...
Page 92: ...Chapter 6 Appendices...
