Chapter 5 Notes on Debugging
Page 5-2
5.1 Chip Differences
The chip at the core of the Oki ML670100 CPU Board differs from the target ML670100 in the
following areas.
5.1.1 User Interface
The Oki ML670100 CPU Board treats certain I/O pins differently from the target
ML670100.
Neither the Angel nor Normal mode supports the primary functions for the following I/O
pins: all PIO0 pins, all PIO1 pins, PIO2.5, and PIO2.6.
The Angel mode supports neither the primary nor secondary functions for the following
I/O pins: PIO5.6 and PIO5.7.
The Normal mode supports neither the primary nor secondary functions for all PIO8
pins except PIO8.2. It also pulls up PIO8.2 with a 100-k
Ω
resistance.
The Oki ML670100 CPU Board also provides additional circuitry for the following
ML670100 pins: AVDD, AGND, VCOM, OSC1, TEST, OSC0, FSEL, PLLEN, VREF,
DBSEL, EA/, EFIQ/ and RESET/.
Summary of Contents for ML670100
Page 16: ...Chapter 1 Read Me First Page 1 12...
Page 79: ...Chapter 4 User Interface Page4 12...
Page 91: ...Chapter 5 Notes on Debugging Page 5 12...
Page 92: ...Chapter 6 Appendices...
