Octek HIPPO II 486 Manual Download Page 41

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CONFIGURING THE SYSTEM
__________________________________

P8 - External Battery Connector

Pin

Assignment

+ Vdc

not used

Ground

KB1 - Keyboard Connector

Pin

Assignment

Keyboard clock

Keyboard data

Spare

Ground

+5 Vdc

JP12 - Connector for Cooling Fan

Pin

Assignment

+5 Vdc

GND

Summary of Contents for HIPPO II 486

Page 1: ...H I P P O I I 4 8 6...

Page 2: ...l in this manual is for information only and is subject to change without notice REVISION 2 2 IBM IBM PC XT AT PC DOS MS DOS OS 2 INTEL AMI ARE THE TRADEMARKS OR REGISTERED TRADEMARKS OF THEIR RESPECT...

Page 3: ...y from the receiver Move the computer away from the receiver Plug the computer into a different outlet so that computer and receiver are on different branch circuits Ensure that card slot covers are i...

Page 4: ...power make sure that all the connectors memory modules and add on cards are secured 3 After power is on wait for a minute The system BIOS are going through a self test during this period and nothing i...

Page 5: ...r 1 contains a brief introduction and specification of OCTEK HIPPO II motherboard In the Chapter 2 the functions of HIPPO II are explained It also outlines many advanced features of the CPU and the sy...

Page 6: ...SYSTEM Installing Math Coprocessor 3 1 Configuration of Cache Memory 3 3 Installing RAM Modules 3 5 Configuration of Memory 3 6 DRAM Configuration 3 7 Control of System Speed 3 8 Reset CMOS Setup Info...

Page 7: ...A 1 System Setup A 4 Appendix B OPERATION AND MAINTENANCE Static Electricity B 1 Keeping The System Cool B 1 Cleaning The Golden Finger B 2 Cleaning The Motherboard B 2 Appendix C TROUBLESHOOTING Mai...

Page 8: ...provides high performance reliability and compatibility to the user OCTEK HIPPO II supports a large secondary cache memory with a write back cache controller Cache size can be 64KB or 256KB Access to...

Page 9: ...re important issues I O channel is compatible to standard AT bus and any peripheral may be used On board POWERGOOD generator is essential to ensure the reliability of the system and is well designed t...

Page 10: ...CATION Processor Intel 80486DX 80486SX or 80487SX CPU with optional WEITEK 4167 Co processor Speed Turbo normal speed I O Slot Compatible to standard AT bus Six 16 bit slots Eight 8 bit slots Secondar...

Page 11: ...for 256KB 1MB or 4MB modules Maximum 64MB on board with optional memory expansion card System Support Functions 8 Channel DMA Direct Memory Access 16 level interrupt 3 programmable timers CMOS RAM fo...

Page 12: ...ic processor and a four way set associate cache memory It is fully binary compatible with 80386 and 80387 All existing software for PC XT AT can be used on OCTEK HIPPO II However due to the new intern...

Page 13: ...GENERAL FEATURES __________________________________...

Page 14: ...emory when CPU reads this data If a read miss occurs the CPU will initiate a burst mode read operation In burst mode read operation CPU performs four successive read operations each of which takes onl...

Page 15: ...e external bus is idle data will be sent to the main memory If all buffers are filled it can start write operation in burst mode Since the internal cache is updated immediately the CPU need not suspen...

Page 16: ...can be increased up to 4GB The demand for sophisticated number crunching scientific and business applications has rapidly increased in recent years In the past microprocessor features an integer Arit...

Page 17: ...erformance to a great extent depends on the data transfer rate In a 80486 system a large portion of the internal cache memory has to be updated to the main memory and then the data for another process...

Page 18: ...s have to share a single memory bus So the less the CPU accesses the main memory the more the external devices is able to use the memory bus In HIPPO II the secondary cache controller is incorporated...

Page 19: ...xternal bus operation will be mostly write operation In a write back cache system the amount of write operations to main memory is minimized The CPU writes the data to the cache memory if the data on...

Page 20: ...GENERAL FEATURES __________________________________ BIOS may be individually selected to be cacheable or not The setup of the non cacheable address ranges can be easily done in the BIOS setup...

Page 21: ...lly detected by the system BIOS So you may easily change the configuration of the system The memory controller system supports page mode The memory is divided into pages with equal size Successive mem...

Page 22: ...esh operations for expansion card on the AT bus and for the main memory are separated To be compatible the refresh operation for AT bus will not be changed But the refresh operation for main memory wi...

Page 23: ...y use different hardware logic design to bypass the keyboard controller Thus the BIOS is needed to be modified to take advantage of it An application without modification may cause problem In HIPPO II...

Page 24: ...speed In HIPPO II a dual bus design is employed A high speed bus links the CPU coprocessor cache memory and main memory This bus is synchronous with clock of the CPU and the data transfer is 32 bits...

Page 25: ...GENERAL FEATURES __________________________________...

Page 26: ...GENERAL FEATURES __________________________________ THIS PAGE IS INTENTIONALLY LEFT BLANK...

Page 27: ...he power before installing or replacing any component INSTALLING MATH COPROCESSOR Math coprocessor WEITEK 4167 is a PGA devices Beside the CPU there is a 144 pin PGA socket To install Math Coprocessor...

Page 28: ...nstalling the Math coprocessor make sure that all the pins are straight The pins are very fragile Once these pins are bent the coprocessor may be damaged The Math coprocessor is automatically detected...

Page 29: ...e external Cache memory Please refer to ADVANCED CMOS SETUP in Appendix A The BIOS will detect the cache memory size automatically and the size will be displayed on the screen before booting The exter...

Page 30: ...U29 and U30 may be installed according to the cache Memory size U28 16Kx4 U29 16Kx4 U30 8Kx8 64K Y Y 64K Y 256K Y Y AT BUS Clock Control JP3 is used to select the AT BUS clock after power up Upon powe...

Page 31: ...gled into the socket s contact and then the module is pivoted into position where the locking latches will secure it If the module edge is not completely inserted into the socket it cannot be pivoted...

Page 32: ...per is needed to be set for the memory size and DRAM type 70ns DRAM is required To determine what DRAM speed rating should be used depends on the system speed and wait state The highest performance is...

Page 33: ...K 1M 5M 256K 256K 1M 6M 1M 1M 8M 256K 1M 1M 9M 256K 256K 1M 1M 10M 1M 1M 1M 12M 256K 1M 1M 1M 13M 1M 1M 1M 1M 16M 4M 16M 1M 4M 20M 4M 1M 20M 1M 1M 4M 24M 1M 4M 1M 24M 4M 1M 1M 24M 1M 1M 1M 4M 28M 1M 4...

Page 34: ...CONFIGURING THE SYSTEM __________________________________ 4M 4M 4M 46M 1M 4M 4M 4M 52M 4M 1M 4M 4M 52M 4M 4M 4M 1M 52M 4M 4M 4M 4M 64M...

Page 35: ...elected the turbo LED of the case will be turned on Whenever the system speed is set to be slow by turbo switch it cannot be changed by the keyboard and vice versa RESET CMOS SETUP INFORMATION Sometim...

Page 36: ...ER SETTING There are several options which allows user to select by hardware switches Display Selection JP9 ON CGA EGA VGA OFF Monochrome display CPU Type 486DX 486SX 487SX JP2 1 2 2 3 1 2 JP3 1 2 2 3...

Page 37: ...The functions of connectors on the motherboard are listed below Description P1 Hardware reset connector P2 Speaker connector P3 Turbo switch P4 Turbo LED P5 Power LED Ext lock connector P6 P7 Power su...

Page 38: ...______________________________ P2 Speaker Connector Pin Assignment 1 Data out 2 5 Vdc 3 Ground 4 5 Vdc P3 Turbo Switch Connector Pin Assignment 1 Selection Pin 2 Ground P4 Turbo LED Connector Pin Assi...

Page 39: ..._ P5 Power LED Ext Lock Connector Pin Assignment 1 5 Vdc 2 Key 3 Ground 4 Keyboard inhibit 5 Ground P6 P7 Power Supply Connector Pin Assignment 1 POWERGOOD 2 5 Vdc 3 12 Vdc 4 12 Vdc 5 Ground 6 Ground...

Page 40: ...CONFIGURING THE SYSTEM __________________________________ 6 5 Vdc...

Page 41: ...__________ P8 External Battery Connector Pin Assignment 1 Vdc 2 not used 3 Ground 4 Ground KB1 Keyboard Connector Pin Assignment 1 Keyboard clock 2 Keyboard data 3 Spare 4 Ground 5 5 Vdc JP12 Connecto...

Page 42: ...CONFIGURING THE SYSTEM __________________________________ THIS PAGE IS INTENTIONALLY LEFT BLANK...

Page 43: ...II MEMORY MAPPING Address Range Function 000000 7FFFFF 000K 512K System Board Memory 512K 080000 09FFFF 512K 640K System Board Memory 128K 0A0000 0BFFFF 640K 768K Display Buffer 128K 0C0000 0DFFFF 76...

Page 44: ...HEX DEVICE 000 01F DMA Controller 1 8237 020 03F Interrupt Controller 1 8259 Master 040 05F Timer 8254 060 06F Keyboard Controller 070 07F Real Time Clock NMI non maskable interrupt mask 080 09F DMA...

Page 45: ...sk 200 207 Game I O 278 27F Parallel Printer Port 2 2F8 2FF Serial Port 2 300 31F Prototype Card 360 36F Reserved 378 37F Parallel Printer Port 1 380 38F SDLC bisynchronous 2 3A0 3AF Bisynchronous 1 3...

Page 46: ...three programmable timer counters controlled by 82C206 and they are defined as channels 0 through 2 Channel 0 System Timer Gate 0 Tied on Clk in 0 1 190 Mhz OSC Clk out 0 8259 IRQ 0 Channel 1 Refresh...

Page 47: ...I bit Clk in 2 1 190 Mhz OSC Clk out 2 Used to drive the speaker Note Channel 1 is programmed to generate a 15 micro second period signal The 8254 Timer Counters are treated by system programs as an a...

Page 48: ...ocessor NMI Parity or I O Channel Check Interrupt Controllers CTLR 1 CTLR 2 IRQ0 Timer Output 0 IRQ1 Keyboard Output Buffer Full IRQ2 Interrupt from CTLR 2 IRQ8 Real time Clock Interrupt IRQ9 Software...

Page 49: ...TECHNICAL INFORMATION __________________________________...

Page 50: ...ACCESS DMA OCTEK HIPPO II supports seven DMA channels Channel Function 0 Spare 8 bit transfer 1 SDLC 8 bit transfer 2 Floppy Disk 8 bit transfer 3 Spare 8 bit transfer 4 Cascade for DMA Controller 1 5...

Page 51: ...el 2 0081 DMA Channel 3 0082 DMA Channel 5 008B DMA Channel 6 0089 DMA Channel 7 008A Refresh 008F REAL TIME CLOCK AND CMOS RAM Real time clock and CMOS RAM are contained on board Real time clock prov...

Page 52: ...rved 12 Fixed disk type byte drives C and D 13 Reserved 14 Equipment byte 15 Low base memory byte 16 High base memory byte 17 Low expansion memory byte 18 High expansion memory byte 19 2D Reserved 2E...

Page 53: ...heir addresses Byte Function Address 0 Seconds 00 1 Second alarm 01 2 Minutes 02 3 Minute alarm 03 4 Hours 04 5 Hour alarm 05 6 Day of week 06 7 Date of month 07 8 Month 08 9 Year 09 10 Status Registe...

Page 54: ...___ SYSTEM EXPANSION BUS OCTEK HIPPO II provides eight 16 bit slots The I O channel supports I O address space from hex 100 to hex 3FF Selection of data access either 8 or 16 bit 24 bit memory address...

Page 55: ...TECHNICAL INFORMATION __________________________________ The following figure shows the pin numbering for I O channel connectors A side and B side...

Page 56: ...TECHNICAL INFORMATION __________________________________ The following figure shows the pin numbering for I O channel connectors C side and D side...

Page 57: ...nel A Side I O Pin Signal Name I O A1 I O CH CK I A2 SD7 I O A3 SD6 I O A4 SD5 I O A5 SD4 I O A6 SD3 I O A7 SD2 I O A8 SD1 I O A9 SD0 I O A10 I O CH RDY I A11 AEN O A12 SA19 I O A13 SA18 I O A14 SA17...

Page 58: ...TECHNICAL INFORMATION __________________________________ A26 SA5 I O A27 SA4 I O A28 SA3 I O A29 SA2 I O A30 SA1 I O A31 SA0 I O...

Page 59: ...B3 5 Vdc Power B4 IRQ9 I B5 5 Vdc Power B6 DRQ2 I B7 12 Vdc Power B8 0WS I B9 12 Vdc Power B10 GND Ground B11 SMEMW O B12 SMEMR O B13 IOW I O B14 IOR I O B15 DACK3 I B16 DRQ3 O B17 DACK1 I B18 DRQ1 O...

Page 60: ...TECHNICAL INFORMATION __________________________________ B30 OSC O B31 GND Ground...

Page 61: ...Channel C Side I O Pin Signal Name I O C1 SBHE I O C2 LA23 I O C3 LA22 I O C4 LA21 I O C5 LA20 I O C6 LA19 I O C7 LA18 I O C8 LA17 I O C9 MEMR I O C10 MEMW I O C11 SD8 I O C12 SD9 I O C13 SD10 I O C14...

Page 62: ...O Channel D Side I O Pin Signal Name I O D1 MEM CS16 I D2 I O CS16 I D3 IRQ10 I D4 IRQ11 I D5 IRQ12 I D6 IRQ15 I D7 IRQ14 I D8 DACK0 O D9 DRQ0 I D10 DACK5 O D11 DRQ5 I D12 DACK6 O D13 DRQ6 I D14 DACK...

Page 63: ...TECHNICAL INFORMATION __________________________________ THIS PAGE IS INTENTIONALLY LEFT BLANK...

Page 64: ...elf test upon reset The test is very intensive and covers all parts of hardware It takes a while before some messages are shown on the screen It does not mean that the system is not working when the s...

Page 65: ...essage 1 DRAM Refresh Failure 2 Base 64KB Memory Parity Error 3 Base 64KB Memory Failure 4 System Time Failure 5 Processor Error 6 Keyboard Controller Gate A20 Failure 7 Processor Exception Interrupt...

Page 66: ...d Disk D Type None Display Type VGA or EGA Serial Port s None ROM BIOS Date 04 15 91 Parallel Port s 3BC Do check the list to make sure that the configuration is correct Sometimes problems arise becau...

Page 67: ...before operating the system Otherwise the system may not run properly with the incorrect setup information Run the setup again if the configuration is changed To enter the setup section press DEL whe...

Page 68: ...ILITIES C 1990 American Megatrends Inc All Rights Reserved STANDARD CMOS SETUP ADVANCED CMOS SETUP AUTO CONFIGURATION WITH BIOS DEFAULTS HARD DISK UTILITY WRITE TO CMOS AND EXIT DO NOT WRITE TO CMOS A...

Page 69: ..._______________ 1 CMOS SETUP The memory size and the numeric processor are detected by the BIOS So you are only required to set those options on the left side of the screen The system configuration in...

Page 70: ...aylight Saving Disabled Cyln Head WPcom LZone Sect Size Hard Disk C type Not Installed Hard Disk D type Not Installed Floppy Drive A 1 2 MB 5 Floppy Drive B 1 44 MB 3 Primary Display VGA or EGA SunMon...

Page 71: ...SYSTEM BIOS __________________________________...

Page 72: ...left and right arrow keys to move between the parameter fields and enter the parameters The parameters will be stored in the CMOS RAM and your fixed disk can be used afterwards Each hard disk can be...

Page 73: ...types of floppy disk drives are supported 1 5 inch standard drive 360K 2 5 inch high density drive 1 2M 3 3 inch standard drive 720K 4 3 inch high density drive 1 44M The system BIOS supports two flo...

Page 74: ...nd VGA 4 Monochrome If the type of display is incorrect the BIOS will prompt you and ask you to set up again But the BIOS is still able to display messages on the display attached to the system Thus y...

Page 75: ...re set to default values by the system BIOS Usually there is no need to modify these registers unless the configuration is changed Since improper settings of these registers may cause the system malfu...

Page 76: ...abled Memory Test Tick Sound Enabled Adapter ROM Shadow E800 16K Disabled Hit DEL Message Display Enabled Adapter ROM Shadow EC00 16K Disabled Hard Disk Type 47 RAM Area 0 300 Adapter ROM Shadow E000...

Page 77: ...SYSTEM BIOS __________________________________...

Page 78: ...for each of the options on the Advanced CMOS Setup Screen If any problem in some options press the F1 Help Key Typematic Rate Programming By enabling this option the user can adjust the rate at which...

Page 79: ...llows you to enter Setup section By default this option is disabled To enter Setup press DEL key before Wait is shown on the screen after warm boot or press it during memory test after power on Hard D...

Page 80: ...the separate area So the option will be ignored System Boot Up Num Lock The num lock option on the keyboard is usually turned on after power on This option allows you to turn the num lock off after po...

Page 81: ...allows you to boot from device A if necessary However it will directly boot from hard disk when selecting C A The BIOS will not read the floppy disk A unless there is no drive C installed Thus it tak...

Page 82: ...ystem at F000H segment BIOS is copied to the on board memory For the option Video ROM the video ROM at C0000H segment or C4000H segment are copied to memory If you install an add on card which ROM BIO...

Page 83: ...some DRAM from various manufacturers can only work with the ordinary refresh period consult your dealer whether this option may be enabled Normally disables this option Single ALE Enable During bus co...

Page 84: ...you set it to Enable an extra wait state will be inserted to every operation to ISA bus It is useful when you find that some slow add on cards are unable to work on HIPPO II Normally select Disable f...

Page 85: ...3 11 2 5 8 10 To be fully compatible set the clock to about 8MHz Non cacheable Block Size and Non cacheable Block Base Two non cacheable block block 1 and block 2 can be defined You need to specify th...

Page 86: ...xadecimal and the size is 32KB This option lets you set the address range to be non cacheable easily without concerning about the base address and the size The default is Disable If the Video BIOS are...

Page 87: ...n with BIOS default is used to set the internal registers of the system in optimum performance with high reliability Once the Auto Configuration is applied the user need not enter the ADVANCED CMOS SE...

Page 88: ...SYSTEM BIOS __________________________________ 5 HARD DISK UTILITY Hard Disk Diagnostics option is taken by pressing Enter at the Main Setup Menu the screen is shown as below...

Page 89: ...American Megatrends Inc All Rights Reserved Cylin Head WPcom LZone Sect Size MB Hard Disk C Type 47 USER TYPE 1314 7 1314 1314 17 76 Hard Disk D Type Not Installed Hard Disk Type can be changed from t...

Page 90: ...SYSTEM BIOS __________________________________...

Page 91: ...he hard drive Your hard disk manual might also include the optimum interleave factor In this case assuming that you have a list of bad tracks and know the interleave factor it will not be necessary to...

Page 92: ...LITY C 1990 American Megatrends Inc All Rights Reserved Cylin Head WPcom LZone Sect Size MB Hard Disk C Type 47 USER TYPE 1314 7 1314 1314 17 76 Hard Disk D Type Not Installed Hard Disk Format Disk Dr...

Page 93: ...SYSTEM BIOS __________________________________...

Page 94: ...If two disk drives have been previously entered at the Standard CMOS Setup Scree then the ID C D will appear to the right of the question mark following the Disk Drive field Choose which drive you wis...

Page 95: ...The default for the Proceed prompt is N to prevent accidental formatting of the hard drive and subsequent loss of data Once this prompt is changed to Y and the ENTER key pressed andy data residing on...

Page 96: ...NTERLEAVE UTILITY The Auto Interleave Utility determines the optimum interleave value by measuring the transfer rate for four different interleave values The cylinders heads and sectors formatted for...

Page 97: ...Y C 1990 American Megatrends Inc All Rights Reserved Cylin Head WPcom LZone Sect Size MB Hard Disk C Type 47 USER TYPE 1314 7 1314 1314 17 76 Hard Disk D Type Not Installed Auto Interleave Bad Track D...

Page 98: ...SYSTEM BIOS __________________________________...

Page 99: ...lysis Utility performs a series of tests to locate bad tracks on the hard disk All bad tracks on the hard disk will be listed in the Bad Track List Box Since this test writes to all cylinders and head...

Page 100: ...ROGRAM HARD DISK UTILITY C 1990 American Megatrends Inc All Rights Reserved Cylin Head WPcom LZone Sect Size MB Hard Disk C Type 47 USER TYPE 1314 7 1314 1314 17 76 Hard Disk D Type Not Installed Medi...

Page 101: ...SYSTEM BIOS __________________________________...

Page 102: ...Hold the cards by their edges KEEPING THE SYSTEM COOL The motherboard contains many high speed components and they will generate heat during operation Other add on cards and hard disk drive can also...

Page 103: ...ard may not work properly Use a pencil eraser to clean the golden finger if dirt is found CLEANING THE MOTHERBOARD The computer system should be kept clean Dust and dirt is harmful to electronic devic...

Page 104: ...d will not be counted by the BIOS It is also a memory failure and you can follow the instruction above CACHE MEMORY FAILURE If the system hangs after memory test it is likely that the cache memory has...

Page 105: ...s after memory test another possible cause is the improper setting of the wait state for memory operation The number of wait state must match the speed of the DRAM Reset the CMOS RAM and set up the wa...

Page 106: ...Appendix D System Board Layout _______________________________...

Page 107: ...Appendix E Memory Expansion Card Layout _______________________________...

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