GENERAL FEATURES
__________________________________
The memory refresh logic is redesigned to
improve the system performance and power
consumption. In the original PC/AT design, the memory
refresh operation will suspend the CPU operation
because it has to access the main memory. In a high
speed system like HIPPO II, the CPU indeed can process a
large amount of operations in the memory refresh
period.
By implementing hidden refresh method, the
refresh operations for expansion card on the AT bus and
for the main memory are separated. To be compatible,
the refresh operation for AT bus will not be changed. But
the refresh operation for main memory will be carried
out individually and will be done when there is no access
to main memory. Furthermore, the frequency of the
main memory refresh operation may be set to 'normal'
or 'slow'. All types of DRAM can be used in `normal'
mode. When 'slow' mode is selected, the availability of
main memory is increased but the refresh period of
DRAM should be longer. Since the refresh period of
DRAM from different manufacturers may vary, consult
your dealer for detail.
Summary of Contents for HIPPO II 486
Page 1: ...H I P P O I I 4 8 6...
Page 13: ...GENERAL FEATURES __________________________________...
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Page 40: ...CONFIGURING THE SYSTEM __________________________________ 6 5 Vdc...
Page 49: ...TECHNICAL INFORMATION __________________________________...
Page 60: ...TECHNICAL INFORMATION __________________________________ B30 OSC O B31 GND Ground...
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Page 71: ...SYSTEM BIOS __________________________________...
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Page 106: ...Appendix D System Board Layout _______________________________...
Page 107: ...Appendix E Memory Expansion Card Layout _______________________________...