Chapter 1 System Overview
Hippo DCA2 User’s Manual
3
1.8
DynamiCache Architecture
The DynamiCache chips are physically similar to a standard 4MB page mode or static
column DRAM with the addition of an integrated Row Register Register and an internal
controller that allows it to operate much like page mode or static column DRAM.
DynamiCache’s Row Register register is tightly coupled with the Memory Array. Memory
Reads always occur from the Row Register Registers. When the internal comparitor
detects a page hit, only the Row Register register is accessed and data is made available in
15ns from the column address. When a page read miss is detected, the new Memory Array
row is loaded into the cache and data is available at the output all within a single 35ns
access. Subsequent reads within the page (burst read, local instructions or data) can
continue at a 15ns cycle time.
Figure 1
Since reads occur from the Row Register register, the Memory Array Precharge can occur
simultaneously without degrading performance. The on chip refresh counter with an
independent refresh bus allows the DynamiCache to be refreshed during cache reads.
Memory Writes are internally posted in 15 nSecs and are directed to the DRAM
array.During a write hit, the on chip comparator activates a parallel write path to the Row
Register register to maintain coherency. The DynamiCache delivers 15nSec page mode
memory writes. This high level of performance is achieved with a single non-interleaved
memory consisting of as few as eight 1M x 4 components or a single 72-pin 4Mbyte
DynamiCache module.
