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Appendix Advanced Technical Information

Hippo DCA2 User’s Manual

A.7

Page Register Address

Page Register

I/O Address (Hex)

DMA Channel 0

0087

DMA Channel 1

0083

DMA Channel 2

0081

DMA Channel 3

0082

DMA Channel 5

008B

DMA Channel 6

0089

DMA Channel 7

008A

Refresh

008F

A.8

System Interrupts

Interrupt Controllers ( NMI level )

Parity or I/O Channel Check

CTLR 1

CTLR 2

IRQ0

Timer Output 0

IRQ1

Keyboard

(Output Buffer Full)

IRQ2

Interrupt from CTLR 2

IRQ8

Real-time Clock Interrupt

IRQ9

Software Redirected to
INT 0AH (IRQ2)

IRQ10

Reserved

IRQ11

Reserved

IRQ12

Reserved

IRQ13

Coprocessor

IRQ14

Fixed Disk Controller

IRQ15

Reserved

IRQ3

Serial Port 2

IRQ4

Serial Port 1

IRQ5

Parallel Port 2

IRQ6

Diskette Controller

IRQ7

Parallel Port 1

Summary of Contents for HIPPO DCA 2

Page 1: ...USER S MANUAL HIPPO DCA 2 VESA LOCAL BUS MOTHERBOARD...

Page 2: ...i Hippo DCA2 486 486 VESA LocalBus Motherboard User s Manual Version 2 25 December 1994...

Page 3: ...e accurate OISI assumesno responsibility in the event that any inaccuracies are found In no event shall OISI be held liable for any loss or expenses whether directly or indirectly caused by the suppor...

Page 4: ...also included in the Appendix for hardware and software engineers This manual provides information about the installation and maintenance of the Octek Hippo DCA2 motherboard In depth explanations conc...

Page 5: ...rnal Cache Saturation Problem 5 1 13 DynamiCache Excels and External Cache Suffers Under Heavy Processing Loads 5 1 14 Target Operating Environments 5 1 15 L2 DCA2 Cache Efficiency Versus Application...

Page 6: ...tor 22 3 16 Turbo Led Connector 23 3 17 Speaker Connector 23 3 18 Keyboard Lock Connector 24 3 19 Keyboard Connector 24 3 20 External Battery Connector 25 3 21 Power Supply Connector 25 Chapter4 BIOS...

Page 7: ...low cost enhancement to standard DRAM DCA2 was designed for pure performance DCA2 transforms the entire memory bank into DynamiCache a high speed memory that operates at 15ns rather than 70ns 1 3 Wha...

Page 8: ...Random Writes 35ns Random Read Access Page Miss Transparent Refresh during Cache Reads Hidden DRAM precharge during Page Reads Consumes 1 3 the power of SRAM plus DRAM solutions On board cache Hit Mi...

Page 9: ...into the cache and data is available at the output all within a single 35ns access Subsequent reads within the page burst read local instructions or data can continue at a 15ns cycle time Figure 1 Sin...

Page 10: ...ion became larger and much more complex supporting virtual disks DLLs and GUI interfaces 1 11 Application Overhead and its effect on External Cache These new applications subsequently brought with the...

Page 11: ...ceases to be effective in providing any benefit to system performance This is the state in which the cache has become saturated If the processing demands from the CPU increase any further the externa...

Page 12: ...usually utilize less than 5 memory load DOS applicationstypically generate less than 25 memory load Windows 3 11 applicationstypically generate approximately 50 memory load OS 2 2 11 UNIX and Windows...

Page 13: ...DRAM modules Memory Width 32 bit DynamiCache DRAM Enhancement Fast Page Mode and Hidden Refresh supported BIOS Subsystem BIOS Type AMI Microid Research BIOS Shadowing Shadow RAM for System and Video B...

Page 14: ...eneral Features Hippo DCA2 User s Manual 8 CHAPTER 2 GENERAL FEATURES 2 1 Layout of Hippo DCA2 Board Figure 2 Inspect and clean your computer system regularly Electronic components are sensitive to du...

Page 15: ...nsion slots 6 32 Bit VESA Extension slots 7 DynamiCache slot 1 and slot 2 8 DRAM slot 1 and slot 2 9 System BIOS 10 Mach 210 programmable logic 11 Mach 110 programmable logic 12 82C802G chipset 13 Tra...

Page 16: ...t state 0 wait state JP13 SL CPU select 2 3 RFU JP14 SL CPU select 2 3 SL JP15 Cyrix CPU support 2 3 RFU JP16 CPU clock multiplier 2 5x open RFU JP17 Clock multiplier 2x open RFU JP18 EPMI open RFU JP...

Page 17: ...of over two hundred authorized distributors worldwide DynamiCache is as easy to handle and install as standard 72 pin DRAM It requires no special handling or skill other than taking normal anti static...

Page 18: ...4 4 16 X 24 4 4 16 4 28 4 4 16 16 40 4 4 32 X 40 4 4 32 32 72 4 8 X X 12 4 8 8 X 20 8 X X X 8 8 X 4 X 12 8 X 4 4 16 8 X 8 X 16 8 X 8 8 24 8 X 16 X 24 8 X 16 4 28 8 X 16 16 40 8 X 32 X 40 8 X 32 32 72...

Page 19: ...miCache to allow the entire program set and dataset to run within DCA2 2 8 ISA Slots ISA is the abbreviation for Industry Standard Architecture It refers to the bus architecture originally created for...

Page 20: ...CPUs as well as various processing speeds With DynamiCache the onboard memory is brought up to the speed of the CPU making it possible to run a fast processor without the problem of bottlenecks 2 11 P...

Page 21: ...he Environmental Protection Agency s Energy Star program In order to meet the EPA s Energy Star standards a system must consume fewer than 30 watts when in sleep mode The Hippo DCA2 accomplishes this...

Page 22: ...system cool The motherboard contains many high speed componentsand they will generate heat during operation Other add on cards and the hard disk can also produce a lot of heat The temperature inside...

Page 23: ...DX4 100 2 3 2 3 1 2 open open 1 2 1 2 3 4 2 3 2 3 2 3 2 3 Intel P24T 2 3 2 3 1 2 open open 1 2 1 2 3 4 2 3 2 3 2 3 2 3 Intel 487 25 1 2 1 2 1 2 open open 2 3 1 2 3 4 2 3 2 3 2 3 2 3 Intel 487 33 2 3 2...

Page 24: ...aight before installing the CPU onto the PGA socket located on your motherboard refer tolayout for exact location To properly align the CPU with thesocket align pin 1 of the CPU with pin 1 of the CPU...

Page 25: ...ks and the DRAM modules into the DRAM banks Figure 9 Memory Modules Sockets Never force the SIMM modules into the SIMM sockets The sockets are fragile and the locking latches may break Depending on ho...

Page 26: ...bank at an angle then push the module forward so that it is locked into place by the latches located on the sides of the bank The latches should be locked tightly and the holes in the module should b...

Page 27: ...w current directly from the motherboard without having to rely on a separate power connector A CPU fan is highly recommended for today shigh speed CPUs Extreme high CPU temperature are generated durin...

Page 28: ...jumpers and dip switches that must be properly set before installing the board into the computer These switches are necessary to configure various functions on the motherboard 3 14 Reset Switch Connec...

Page 29: ...oggle between standard AT Bus speed and maximum speed of the processor This switch is open when it s ready for normal operation and is closed or shorted to obtain high speed of the sytem 1 2 Figure 12...

Page 30: ...nector and can be installed in keyed position 3 18 Keyboard Lock Connector The keyboard lock enables the user to lock the keyboard preventing unauthorized use of the system J is a five pin single in l...

Page 31: ...cards Before turning on the power make sure that all of these parts are secured 3 20 External Battery Connector The Hippo DCA2 comes with an onboard rechargeable battery so an external battery is not...

Page 32: ...y provide 5 VDCwith a voltage range between 4 95 VDC and 5 25 VDC There are two power supplies connectors on the motherboard Power supplies can run on a widerange of voltages and must be set to the pr...

Page 33: ...ailure The memory refresh circuitry is faulty 2 Parity Error A parity error occured in the first 64KB block of memory 3 Base 64K RAM Failure A memory failure occurred in the first 64KB of memory 4 Sys...

Page 34: ...L H L Memory bank 0 block access read failure L H L H H L Memory bank 0 block access read wrfitge failure L H H H H L Master 8259 failure L H L L L H Slave 8259 failure L H H L L H Master 8259 interr...

Page 35: ...128 KB Video RAM display buffer 00C0000 00DFFFF 128 KB Reserved for add on cards ROM BIOS 00E0000 00EFFFF 64 KB System ROM BIOS expansion 00F0000 00FFFFF 64 KB System ROM BIOS 0100000 0FDFFFF 15232 K...

Page 36: ...DMA Page Registers 0A0 0BF Interrupt Controller 2 8259A 0C0 0DF DMA Controller 2 8237A 5 0F0 Clear Math Coprocessor Busy 0F1 Reset Math Coprocessor 0F8 0FF Math Coprocessor 1F0 1F8 Fixed Disk 200 207...

Page 37: ...O CLK B20 A20 SA11 I O I IRQ7 B21 A21 SA10 I O I IRQ6 B22 A22 SA9 I O I IRQ5 B23 A23 SA8 I O I IRQ4 B24 A24 SA7 I O I IRQ3 B25 A25 SA6 I O O DACK2 B26 A26 SA5 I O O T C B27 A27 SA4 I O O BALE B28 A28...

Page 38: ...round B24 A24 CA27 CA24 B25 A25 CA25 CA22 B26 A26 CA23 Power B27 A27 CA21 CA20 B28 A28 CA19 CA18 B29 A29 Ground CA16 B30 A30 CA17 CA14 B31 A31 CA15 CA12 B32 A32 Power CA10 B33 A33 CA13 CA8 B34 A34 CA1...

Page 39: ...t address C2 CH 0 base and current word count C4 CH 1 base and current address C6 CH 1 base and current word count C8 CH 2 base and current address CA CH 2 base and current word count CC CH 3 base and...

Page 40: ...008F A 8 System Interrupts Interrupt Controllers NMI level Parity or I O Channel Check CTLR 1 CTLR 2 IRQ0 Timer Output 0 IRQ1 Keyboard Output Buffer Full IRQ2 Interrupt from CTLR 2 IRQ8 Real time Clo...

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