OCI BDL800IR, Instruction Manual

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18 Chapter 4 Electronics
A lock-in amplifier for phase sensitive detection is built into this unit. It consists of one
phase-locked loop (PLL), one phase sensitive detector (PSD), two single-ended analog-to-
digital converters (ADC), and two digital-to-analog converters (DAC). Also available are
four lines for digital input and four lines for digital output. The PLL can be set to lock either
on the fundamental or the second harmonic.
Sensitivity, time constant, and phase are controlled externally by the AES software. The
phase can be adjusted to 90° or 180°.
4.2.1 Detail Description
High Voltage Ramp Generator
Sweep Generator Sweep Voltage 0–2000 V
Sweep Rate AES software controlled (16-bit DAC)
Sweep Voltage Offset
(start) AES software controlled (16-bit DAC)
Sweep Voltage Offset
(end) AES software controlled (16-bit DAC)
Ramp Voltage Moni-
tor AES software controlled (16-bit DAC)
Internal Oscillator and
Modulator Frequency Fixed at 1.457 kHz, trimmer adjusted ±5%
Amplitude (peak-to-
peak) Regulated from 0.5 to 20 V (16-bit DAC)
Distortion Harmonic 0.1%
Noise 50 μV RMS
PSD Type Switching multiplier
Input Impedance AC coupled, 100 nF into 1 MΩ
Input True differential
AC Gain 10, 100, 1000, 10000 (and 1, 2, 4, 8) software
selectable
Interstage Coupling
Simple high pass typically with  3 dB per
72 Hz
Post Detection Low
Pass Filter Equal component Sallen-Key, 2
nd
order with
a time constant of 0.1, 0.5, 1, and 3 s
Signal Channel
Equivalent Input Typically less than 20 nV/Hz at 1 kHz