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NyQuest Innovation Labs NY6 Series User Manuel Download Page 81

 

NY6 User Manual

 

 

 

 

 

Ver  1.3      2019/03/28

 

81

 

RDPC

 

Function :  Read program counter (PC) to RPT 
Operation : 

RPT[21:0] ←  PC

 

Operand : 

None 

Words : 

1 

Cycles : 

1 

Operative Flags: None 
Flags Affected: None 
Example : 

   RBPC 

Before Instruction 

RPT= 0x????? 
PC = 0x012035 

After Instruction 

RPT = 0x012035

 

 
 
 
 

LDSPRH

 

Function :  Load  MSB 12-bit address for SPI flash. 

The address should be loaded in RPT 
firstly. 

Operation : SPR [23:12] 

← RPT[11:0]

 

Operand : 

None 

Words : 

1 

Cycles : 

1 

Operative Flags: None 
Flags Affected: None 
Example : 

MVLA   0x2 

MVAM RPT0 
MVLA  

0x3 

MVAM RPT1 

MVLA  

0x4 

MVAM RPT2 
LDSPRH 

Before Instruction 

SPR = 0x000000 

After Instruction 

SPR = 0x432000

 

 

RDSPRH

 

Function :  Read  MSB 12-bit address for SPI flash. 

The address should be loaded in RPT 
firstly. 

Operation : 

RPT[11:0] ←

 SPR [23:12] 

Operand : 

None 

Words : 

1 

Cycles : 

1 

Operative Flags: None 
Flags Affected: None 
Example : 

    RDSPRH 

Before Instruction 

RPT = 0x000 
SPR = 0x432765 

After Instruction 

RPT = 0x432

 

 
 

LDSPRL

 

Function :  Load LSB 12-bit address for SPI flash. The 

address should be loaded in RPT firstly. 

Operation : SPR [11:0] 

← RPT[11:0]

 

Operand : 

None 

Words : 

1 

Cycles : 

1 

Operative Flags: None 

Flags Affected: None 

Example : 

    MVLA  0x5 

MVAM RPT0 

MVLA  

0x6 

MVAM RPT1 

MVLA  

0x7 

MVAM RPT2 

LDSPRH 

Before Instruction 

SPR = 0x000000 

After Instruction 

SPR = 0x000765

 

Summary of Contents for NY6 Series

Page 1: ...document Contact NYQUEST to obtain the latest version of device specifications before placing your orders No responsibility is assumed by NYQUEST for any infringement of patent or other rights of thir...

Page 2: ...1 0 2016 08 31 Formal release 1 1 2016 11 25 1 Modify pad description 2 Update DC characteristics 3 Fix typos 10 11 1 2 2017 05 17 1 Add description that a 0 1uF power capacitor nearby PB_VDD is neces...

Page 3: ...14 2 3 1 Power On Reset POR 14 2 3 2 Low Voltage Reset LVR 14 2 3 3 Watch Dog Timer Reset WDTR 14 2 3 4 I O Port External Reset 14 2 4 Address Pointer 15 2 4 1 Program Counter PC 15 2 4 2 Stack STK 15...

Page 4: ...Chapter 3 System Control 30 3 1 Introduction 30 3 1 1 System Register Address Map 30 3 1 2 Memory Register Address Map 33 3 2 RPT 33 3 3 ROD 34 3 4 INTx INTFx 0 03 34 3 5 BTF 04 34 3 6 ONOFF 05 35 3 7...

Page 5: ...ody Playback Tail Only Mode 48 3 17 4 Melody Playback Head Tail Mode 51 3 17 5 Ramp up Ramp down Procedure for DAC 55 3 18 Power Saving Mode 58 3 18 1 Slow Mode 58 3 18 2 Halt Mode 58 Chapter 4 Instru...

Page 6: ...speech or melody that is tailored for applications of volume adjustment NY6 provides two kinds of audio outputs with fine resolution one is 12 bit current type D A converter DAC and the other is 12 b...

Page 7: ...access Dual power system operation supported ex NY6 5V SPI 3V Up to 24 flexible Bi direction I Os Direction of each I O is independently controlled by individual register bit Each Bi direction I O pin...

Page 8: ...eech or MIDI channel New high fidelity 4 bit 5 bit mixed ADPCM or 10 bit PCM speech synthesis algorithm and ADSR with 256 step envelope for MIDI synthesis Patented noise filtering algorithm with 250KH...

Page 9: ...11A 11 7 32K x 10 32K x 10 16 12 bit 12 bit NY6B018A 18 3 48K x 10 48K x 10 16 12 bit 12 bit NY6B025A 25 64K x 10 64K x 10 16 12 bit 12 bit NY6B035A 35 88K x 10 64K x 10 16 12 bit 12 bit NY6B045A 45 1...

Page 10: ...wer Power for PBx and external component Not available for NY6A PB0 CSb I O Bit 0 for Port B or chip select pin for SPI interface PB1 SCK I O Bit 1 for Port B or serial clock pin for SPI interface PB2...

Page 11: ...84ms no load 4 5 80 IOP Normal mode 3 0 1 8 mA 2MHz no loading 4 5 5 0 IIL Input current Internal pull high Weak 1 2M ohms 3 0 2 5 uA VIL 0V 4 5 7 4 Strong 100k ohms 3 0 30 uA 4 5 75 IOH Output high c...

Page 12: ...ice Tail pointer according to CHNM DPR0 7 Data pointer share with STK7 0 STK0 7 8 level interrupt dedicated stack share with DPR0 7 PC Program counter RPT Multi function register pointer M 0x0 0x5 XMD...

Page 13: ...C 0xD INTx Interrupt generator T 0x0 0x1 LVD Low Voltage Detector T 0x0A SYS Reset System reset generator POR Power reset generator LVR Low Voltage Reset ACC 4 bit accumulator ALU 4 bit arithmetic log...

Page 14: ...IC When the detector detects a harmful low voltage supply it will cause a low voltage reset The so called low voltage point of the NY6 IC is approximate 1 9V RAM Pages5 3E 3F are optioned to be protec...

Page 15: ...tructions which are listed in table below The interrupt vector is at address 0x000010 Inst Event Function JMP Addr Jump to BANK Addr CALL Addr Push the PC 2 to the STK and load BANK Addr to PC Interru...

Page 16: ...bit width are necessary for playing speech or MIDI of each channel When PLAY is executed the system loads RPT to HVPR of the channel that assigned by the CHNM register When LDSEC is executed the syste...

Page 17: ...LU Instruction Summary 2 5 1 1 Logic Instruction Instruction Function Flag Influenced XORM m A M m A Z ANDM m A M m A Z XORL L A L A Z ANDL L A L A Z ORL L A L A Z RRC Right Rotate A with C C Z RLC Le...

Page 18: ...register 0x0 0x3 related to interrupt execution The width of b is 2 bit for bit address of system register to execute clear or set desired bit by INTCB and INTSB The width of the RAM address m of inst...

Page 19: ...lt is larger than 0xF C 1 and C 0 if the result is 15 If the subtraction operation smaller than 0 C 0 and C 1 if the result 0 2 6 Memory Organization There are maximum 1728K words ROM 6x56 nibbles of...

Page 20: ...high resistor or input with register controlled pull high resistor high to low wakeup only If users want to enable disable pull high resistor by register during program execution only high to low leve...

Page 21: ...data to play only for channel 0 Users have to finish a sequence of setting steps for voice pattern and set PLAY For details please refer to Chapter 2 10 2 7 1 Pull High Input Mode Pull high Input Mode...

Page 22: ...r controlled pull high Normal large or constant current output PA2 IR IR carrier output or Normal I O Input with pull high floating or register controlled pull high Normal large or constant current ou...

Page 23: ...O Input with pull high floating or register controlled pull high Normal large or constant current output PBx PCx PDx PEx PFx Normal I O Input with pull high floating or register controlled pull high...

Page 24: ...s by INT1 There is a difference from BT those interrupt flags will be able to read back even if entrance is turned off In other words the flag is launched while the event is triggered and the procedur...

Page 25: ...the internal LDO regulator it powers external flash and Port PB 10mA 3V Users have to enable internal LDO by SPIV before transmitting data or else the power for SPI interface sill be abnormal Unless...

Page 26: ...earby PB_VDD pin is necessary to stabilize the voltage if LDO regulator is enabled 2 13 Low Voltage Detector LVD There is one hardware voltage detector in NY6 It offers four levels for various applica...

Page 27: ...e periodic wave repeatedly The ROM occupied by this kind of patch is minimal however sound quality is sacrificed The compromise architecture is Head Tail with envelope information which is called ADSR...

Page 28: ...ut user can choose one of the 12 bit DAC or 12 bit PWM as the audio output for NY6 series If DAC is selected ramp up process has to be implemented by user s application program If PWM is selected ther...

Page 29: ...nformation is 8 bit the envelope data of selected channel will not be updated until LDEN is executed User can refer Chapter 3 8 6 for details 2 14 6 Volume Control NY6 supports 16 step digital volume...

Page 30: ...M access with different addressing composed by RPT and PAGE The SPIV register is for power control for SPI interface and SPIC register is for further SPI control The SPIDx registers are used to access...

Page 31: ...le 3 2 Reserved 0 08 DECMD1 R 1 0 00 Head ADPCM 4 bit Mode 4 bit 01 Head ADPCM 5 bit Mode 1x Head PCM Mode 3 2 00 Tail ADPCM 4 bit Mode 4 bit 01 Tail ADPCM 5 bit Mode 1x Tail PCM Mode 09 VOL R W 3 0 0...

Page 32: ...te to port A output register xxxx 15 PAIO R W 3 0 0 1 Port A direction Output Input Input 16 PB R 3 0 0 1 PBIO 1 Read port B input pad data xxxx PBIO 0 Read port B output register xxxx W 3 0 0 1 PBIO...

Page 33: ...s register xxxx 7 ROD2 R W 1 0 0 1 ROM 9 8 data access register xx 3 2 RPT As RPT have 6 registers and memory access may need up to 21 bits RPT 3 0 is mapped to RPT0 RPT 7 4 is mapped to RPT1 RPT 11 8...

Page 34: ...6 384ms The INTF1 register is for four kinds of interrupt source Timer counter TM flag issued as counter overflow PHC flag issued as PH counter overflow and only set for channel 1 SPI flag issued as S...

Page 35: ...oltage level The precision of level at 4 1V will be controlled in 5 and other levels less than 5 3 8 TMCS 0B The TMCS register is used to select timer clock source and define timer value RTMx applied...

Page 36: ...rnal LDO regulator or external VDD The SPIV 1 bit is to enable LDO regulator and the default is disable The SPIV 2 bit is also read only and represents the result of comparator and SPIV 3 bit is reser...

Page 37: ...ke up NY6 from Halt mode or Slow mode Therefore user has to read the I O pin state before entering Halt mode or Slow mode and write back to register PX y X A F y 0 3 When 1 is written to register PX y...

Page 38: ...e used to control audio format for each channel x 0 or 1 For access of both registers the referenced channel should be specified by instruction CHNO first to avoid setting to wrong channel The DECMD0...

Page 39: ...ay Flag of CH 0x00 PFLG R 1 1 bit Play Flag of CH 0x00 PH RW 12 12 bit PH value of CH 0x000 MIXDT R 12 12 bit Mixer data 0x000 3 16 1 BANK The bank register is used to switch the program bank when the...

Page 40: ...ted is by instruction LDEN and the ENV will be loaded by RPT 7 0 RPT1 RPT0 Also ENV is able to read back by instruction RBEN and the RPT 7 0 is the register which saves envelope value Note that the en...

Page 41: ...ely and PF flag will become 0 3 16 7 PH Value Setting PH is a 12 bit value which represents how much relative time is elapsed from last playback sample based on ratio of sample rate to system clock Th...

Page 42: ...Voice INCLUDATA Demo v6x 2 Setup Total Playback Channel The total number of playback channel can be 2 4 6 or disable and this value will determine PH setting and volume setting accordingly Once playba...

Page 43: ...ad Waveform and Voice File Format As voice is played only is Head waveform allowed The file format of voice file could be PCM ADPCM4 or ADPCM5 9 Determine PH value PH value is determined according to...

Page 44: ...Envelope MVAM RPT0 MVAM RPT1 LDEN MVLA 0x01 Set Voice Interpolation Tail Disable Encode Mode MVAT DECMD0 MVLA 0x02 MVAT DECMD1 MVLA 0x0B Set Voice PH Value Voice S R 12K MVAM RPT0 MVLA 0x09 MVAM RPT1...

Page 45: ...LIGN 0x10 L_Head INCLUDATA Piano_Head v6x 2 Setup Total Playback Channel The total number of playback channel can be 2 4 6 or disable and this value will determine PH setting and volume setting accord...

Page 46: ...ble 8 Setup Head Waveform File Format As Head Only mode is adopted Tail waveform is disabled The file format of patch file could be PCM or ADPCM5 9 Determine PH value PH value is determined according...

Page 47: ...annel Volume Envelope MVAM RPT0 MVAM RPT1 LDEN MVLA 0x01 Set Note Interpolation Tail Disable Encode Mode MVAT DECMD0 MVLA 0x02 MVAT DECMD1 MVLA 0x0C Set Note PH Value MVAM RPT0 MVLA 0x02 MVAM RPT1 MVL...

Page 48: ...LIGN 0x10 L_Tail INCLUDATA Piano_Tail v6x 2 Setup Total Playback Channel The total number of playback channel can be 2 4 6 or disable and this value will determine PH setting and volume setting accord...

Page 49: ...be PCM or ADPCM5 9 Determine PH value PH value is determined according to formula PATCH NOTE INST F F F 4096 CH 8 SR For example patch SR 22 050 Hz CH 2 FINST 2 000 000 FPATCH is G3 196 0 Hz FNOTE is...

Page 50: ...Set Channel Volume Envelope MVAM RPT0 MVAM RPT1 LDEN MVLA 0x03 Set Note Interpolation Tail Enable Encode Mode MVAT DECMD0 MVLA 0x0A MVAT DECMD1 MVLA 0x0C Set Note PH Value MVAM RPT0 MVLA 0x02 MVAM RP...

Page 51: ...must be aligned with specific address whose last 4 bits must be all zeros ORGALIGN 0x10 L_Head INCLUDATA Piano_Head v6x ORGALIGN 0x10 L_Tail INCLUDATA Piano_Tail v6x 2 Setup Total Playback Channel Th...

Page 52: ...ct interpolation function enable or disable 8 Setup Waveform File Format As Head Tail mode is adopted Tail waveform is enabled too The file format of patch file could be PCM or ADPCM5 The combination...

Page 53: ...d INCLUDATA Piano_Head v6x ORGALIGN 0x10 L_Tail INCLUDATA Piano_Tail v6x 3 17 4 3 Example Code of Head Tail Melody Playback L_START MVLA 0x09 Set Total Playback Channel Audio Output MVAT CHARC MVLA 0x...

Page 54: ...ail MVAM RPT2 MVLA Mid1 Tail MVAM RPT3 MVLA High0 Tail MVAM RPT4 MVLA High1 Tail MVAM RPT5 LDSEC MVLA Low0 Tail Set Head Wave Address Execute PLAY Instruction MVAM RPT0 MVLA Low1 Head MVAM RPT1 MVLA M...

Page 55: ...p up and one ramp down wav data and encode them with command Encode Ramp Up Down Table in PCM format by Voice_Encoder and stored them in V6x format It is recommended that length of ramp up ramp down w...

Page 56: ...d Wave Address Execute PLAY Instruction MVAM RPT0 MVAM RPT1 MVLA 0x05 MVAM RPT2 MVLA 0x02 MVAM RPT3 MVLA 0x01 MVAM RPT4 MVLA 0x00 MVAM RPT5 PLAY RBCH INCA JMP L_RampUpChannelLoop L_RampUpEnd ORG 0x125...

Page 57: ...Set Note PH Value MVAM RPT0 MVLA 0x02 MVAM RPT1 MVLA 0x06 MVAM RPT2 MVLA 0x00 MVAM RPT3 LDPH MVLA 0x00 Set Head Wave Address Execute PLAY Instruction MVAM RPT0 MVAM RPT1 MVLA 0x05 MVAM RPT2 MVLA 0x02...

Page 58: ...the SLOW instruction will be executed immediately On the other hands after IC is waked up by the interrupt of BT its interrupt service routine will be executed immediately Remember to turn off the au...

Page 59: ...L 4L A A L 1 1 Z 16 XORL 4L A A L 1 1 Z 17 MVLA 4L A L 1 1 18 INTCB 2t 2b Clear T b 1 1 19 INTSB 2t 2b Set T b 1 1 20 INCA C A A 1 1 1 C Z 21 DECA C A A 1 1 1 C Z 22 RRC Right Rotate A with C 1 1 C C...

Page 60: ...Table Read of CHNM 3 1 Other Instructions 56 CALL 16a Call Adr 2 2 57 JMP 16a Jump Adr 2 2 58 BANK 3bk Set 3 bit Bank 512K 1 1 59 MPG 3p Move Page to MPG 1 1 60 RBSPRH Read SPR 23 12 to RPT 11 0 1 1 6...

Page 61: ...pointer of CHNM ENV 8 bit envelope data of CHNM ROM 10 bit ROM data ROD ROM data access register data PC Program counter address pointer DPR Data address pointer STK Interrupt dedicated stack address...

Page 62: ...er or SRAM to subtract with 0x0 to 0x3F B 1 bit borrow flag data shared with carry flag B C Words 1 Cycles 1 Operative Flags C Flags Affected C Z Example SUBM m0 Before Instruction ACC 0xA m0 0x2 C 1...

Page 63: ...ter or SRAM to OR with 0x0 to 0x3F Words 1 Cycles 1 Operative Flags None Flags Affected Z Example ORM m0 Before Instruction ACC 0x3 m0 0xB After Instruction ACC 0xB m0 0xB Z 0 MVAM m Function Move ACC...

Page 64: ...of System register 0x00 to 0x3F Words 1 Cycles 1 Operative Flags None Flags Affected None Example MVAT t0 Before Instruction ACC 0x8 After Instruction t0 0x8 MVTA t Function Move M of address m to AC...

Page 65: ...B 1 bit borrow flag data shared with carry flag B C Words 1 Cycles 1 Operative Flags C Flags Affected C Z Example SUBL 0x2 Before Instruction A 0xA L 0x2 C 1 After Instruction A 0x8 Z 0 C 1 ANDL L Fun...

Page 66: ...ation to set to 1 Words 1 Cycles 1 Operative Flags None Flags Affected None Example INTSB t2 0x2 Before Instruction t2 0x0 After Instruction t2 0x4 XORL L Function Exclusive OR ACC with immediate cons...

Page 67: ...one Words 1 Cycles 1 Operative Flags C Flags Affected C Z Example RRC Before Instruction ACC 0x3 C 1 After Instruction ACC 0x9 C 1 Z 0 RLC Function Left rotate ACC with Carry Operation ACC 3 0 C C ACC...

Page 68: ...ction ACC 0x3 Z 0 After Instruction ACC 0x6 Z 0 SETC Function Set Carry bit to 1 Operation C 1 Operand None Words 1 Cycles 1 Operative Flags None Flags Affected C Example SETC Before Instruction C 0 A...

Page 69: ...3 4 Operative Flags None Flags Affected None Example SALT 0x8 Inst1 Inst2 After Instruction If ACC or 0x8 Inst1 is executed If ACC 0x8 Inst1 is discarded and Inst2 is executed SAEL L Function Skip the...

Page 70: ...mple SCNZ Inst1 Inst2 After Instruction If C 0x 1 Inst1 is executed If C 0x 1 Inst1 is discarded and Inst2 is executed SZNZ Function Skip the next instruction if Zero equal to 1 Operation Skip next if...

Page 71: ...1 0x010234 PFLG 0x1 1 LDSEC Function Load Tail wave address for the channel indexed by the CHNM register The Tail wave address should be loaded in TREG 19 0 firstly Operation TVPR CHNM RPT Operand Non...

Page 72: ...T1 MVLA 0x3 MVAM RPT2 MVLA 0xD MVAM RPT3 MVLA 0x1 MVAM RPT4 MVLA 0x0 MVAM RPT5 LDPR Before Instruction DPR 0x2 0xXXXXX After Instruction DPR 0x2 0x01D390 LDPH Function Load PH value to the channel ind...

Page 73: ...s None Flags Affected None Example MVLA 0x2 CHNO RBEN Before Instruction ENV 0x2 0x2E After Instruction RPT 0x2E RBVPR Function Read HVPR voice pointer content The HVPR to read is indexed by the CHNM...

Page 74: ...ter Operation CHNM ACC Operand None Words 1 Cycles 1 Operative Flags None Flags Affected None Example MVLA 0x5 CHNO Before Instruction CHNM 0xX After Instruction CHNM 0x5 RBCH Function Read CHNM regis...

Page 75: ...OD1 0x3 ROD2 0x1 and DPR 0x1 data0 RDNI Function Read ROM data using the DPR data pointer indexed by the CHNM register and increase the DPR after data reading Operation ACC bit 3 0 of read data ROD1 b...

Page 76: ...on If all channel play Inst1 is executed If all channel not play Inst1 is discarded and Inst2 is executed STOP Function Stop voice Head wave or Tail wave playing on the channel indexed by the CHNM reg...

Page 77: ...jump by direct address Operation PC BANK a Operand a 16 bit program address to jump 0x0000 to 0xFFFF Words 2 Cycles 2 Operative Flags None Flags Affected None Example JMP a1 Before Instruction PC a0...

Page 78: ...Flags None Flags Affected None Example CLI Before Instruction Interrupt entrance is enable After Instruction Interrupt entrance is disable RET Function Return from subroutine Operation PC STK Operand...

Page 79: ...n about 14 3 times CWDT0 Function Clear Watch Dog Timer Step1 Operation Step1 for clear Watch Dog Timer Operand None Words 1 Cycles 1 Operative Flags None Flags Affected None Example CWDT0 Before Inst...

Page 80: ...ion No operation Operation None Operand None Words 1 Cycles 1 Operative Flags None Flags Affected None Example NOP After Instruction No operation for 1 cycle LDPC Function Load program counter PC with...

Page 81: ...VLA 0x4 MVAM RPT2 LDSPRH Before Instruction SPR 0x000000 After Instruction SPR 0x432000 RDSPRH Function Read MSB 12 bit address for SPI flash The address should be loaded in RPT firstly Operation RPT...

Page 82: ...SB 12 bit address for SPI flash The address should be loaded in RPT firstly Operation RPT 11 0 SPR 11 0 Operand None Words 1 Cycles 1 Operative Flags None Flags Affected None Example RDSPRL Before Ins...

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