NY6 User Manual
Ver 1.3 2019/03/28
18
2.5.1.3 Data Transfer Instruction
Instruction
Function
Flag Influenced
MVAM m
M[m]
←
A
MVMA m
A
←
M[m]
Z
MVAT t1
T[t1]
←
A
MVTA t1
A
←
T[t1]
Z
MVLA L
A
←
L
INTCB t2, b Clear T[t2][b]
INTSB t2, b Set T[t2][b]
SETC
C
←
1
C
CLRC
C
←
0
C
M[m] : 4-bit RAM data at memory address m1, 0x00
≤
m
≤
0x3F.
T[t1] : 4-bit system register data at address t1, 0x0
≤
t1
≤
0x1F
T[t2] : 4-bit system register data at address t2, 0x0
≤
t2
≤
0x3
b : bit address,
0x0
≤
b
≤
0x3
The width of the system register address ‘t1’ of MVAT and MVTA instruction is 5-bit (0x00~0x1F),
and address ‘t2’ of INTCB and INTSB instruction is 2-bit, to access system register 0x0~0x3 related
to interrupt execution. The width of ‘b’ is 2-bit for bit address of system register to execute clear or
set desired bit by INTCB and INTSB. The width of the RAM address `m’ of instructions associated
with memory operation is 6-bit. Only 0x00~0x07 registers are independent of SRAM page. Users
can use memory-related instructions to handle RAM of address 0x08~0x3F, but the RAM page is
still working.
2.5.1.4 Conditional Branch Instruction
Instruction
Function
Flag Influenced
SAGT L
Skip when A > L
SALT L
Skip when A < L
SANE L
Skip when A != L
SCEZ
Skip if C = 0
SZEZ
Skip if Z = 0
SCNZ
Skip if C != 0
SZNZ
Skip if Z !=0
SBZ b
Skip when A[b] = 0
SNP
Skip when Play = 0, according to CHNM
SP
Skip when Play = 1, according to CHNM.
SANP
Skip when ALL 6 channels Play = 0
SNHP
Skip when head Play = 0, according to CHNM.