NyQuest Innovation Labs NY6 Series, User Manuel

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NY6 User Manual
Ver 1.3 2019/03/28 33
Addr Name R/W Bit Data Description Default
W [3:0] 0/1
PEIO = 1: Wake-up Status (Option Disable)
PEIO = 1: Floating / Pull-high (Option Enable)
wakeup
status
PEIO = 0: Write to port A output register xxxx
$1D PEIO R/W [3:0] 0/1 Port E direction = Output / Input Input
$1E PF
R [3:0] 0/1
PFIO = 1: Read port F input pad data xxxx
PFIO = 0: Read port F output register xxxx
W [3:0] 0/1
PFIO = 1: Wake-up Status (Option Disable)
PFIO = 1: Floating / Pull-high (Option Enable)
wakeup
status
PFIO = 0: Write to port A output register xxxx
$1F PFIO R/W [3:0] 0/1 Port F direction = Output / Input Input
3.1.2 Memory Register Address Map
Addr Name R/W Bit Data Description Default
$0 RPT0 R/W [3:0] 0/1 Multi-function register pointer [3:0] ‘b0000
$1 RPT1 R/W [3:0] 0/1 Multi-function register pointer [7:4] ‘b0000
$2 RPT2 R/W [3:0] 0/1 Multi-function register pointer [11:8] ‘b0000
$3 RPT3 R/W [3:0] 0/1 Multi-function register pointer [15:12] ‘b0000
$4 RPT4 R/W [3:0] 0/1 Multi-function register pointer [19:16] ‘b0000
$5 RPT5 R/W [0] 0/1 Multi-function register pointer [20] ‘b0
$6 ROD1 R/W [3:0] 0/1 ROM[7:4] data access register xxxx
$7 ROD2 R/W [1:0] 0/1 ROM[9:8] data access register xx
3.2 RPT
As RPT have 6 registers and memory access may need up to 21 bits, RPT[3:0] is mapped to RPT0,
RPT[7:4] is mapped to RPT1, RPT[11:8] is mapped to RPT2, RPT[15:12] is mapped to RPT3, RPT[19:16]
is mapped to RPT4, RPT[20] is mapped to RPT5[0] and RPT5[3:1] are not used and read back “0”.
The RPT of NY6A and NY6B is 18-bit long, and the NY6C’s RPT is 21-bit. The redundant bits of RPT
(RPT[20:18] of NY6A and NY6B) are un-writable and un-know if users read them. The RPT5 is 1-bit and
its allocation is [0]. The functions of RPT are listed in the section 2.4.3.
Besides the instructions related to the LDPH only access bit [11:0] of the RPT, the RBDA only access bit
[11:8] of the RPT, the LDEN only access bit [7:0] of the RPT, the XMD0 access bit [5:0] of RPT and the
XMD1 only access bit [13:8] of the RPT, others instructions require all 18 or 21 bits available at RPT
registers. The RPT will be frequently accessed because of its multi-functionality.
The SPI-related instructions, such RBSPRH, RBSPRL, LDSPRH and LDSPRL, access RPT twice for 24-
bit addressing allocation for SPI flash. The RBSPRx is for reading 24-bit address, LDSPRx is for writing
24-bit address to RPT, “H” is for MSB 12-bit and ”L” is for LSB 12-bit data access.