NY6 User Manual
Ver 1.3 2019/03/28
58
3.18 Power Saving Mode
Reset
procedure
Slow mode
Halt mode
Normal mode
Power on
Reset
Reset
Reset
Reset procedure done
Wake-up
Wake-up
SLOW
HALT
Power Saving Mode Flow Chart
3.18.1 Slow Mode
The system enters the Slow mode if the SLOW command is executed. The system clock in the Slow
mode is about 14.3 (+/-3%) times slower than in the Normal mode. The difference between the Halt
mode and the Slow mode is only the system clock. So the IC can be waked-up from the Slow mode by
the interrupt in addition to the input port level change. In Slow mode, there are 4 kinds of base timer
intervals for polling: 3.661ms, 7.322ms, 14.643ms and 234.291ms.The wake-up stable time from Slow
mode is about 50us.
The input wake-up manner is the same as the Halt mode. So before executing the SLOW instruction,
users have to keep in mind to store the current input port statuses into port registers. If NY6 is waked-up
from the Slow mode by an external reset signal, it goes into the reset procedure. After IC is waked-up
by the input port level change, the next instruction after the SLOW instruction will be executed
immediately. On the other hands, after IC is waked-up by the interrupt of BT, its interrupt service routine
will be executed immediately. Remember to turn off the audio output before entering to the slow mode.
3.18.2 Halt Mode
The system enters the Halt mode if the HALT command executed. The halt mode is also known as the
Sleep mode. As implied by the name, the IC falls asleep and the system clock is completely turned off,
so all the IC functions are halted and it minimizes the power consumption.
The only way to wake-up the system from Halt mode is an input port level change wake-up. The IC
keeps monitoring the input pads during the Halt mode. If the input status of any input pad differs from
the corresponding port register, the system will be waked-up. Then the next instruction after the HALT
instruction will be executed after the wake-up stable time (about 50us) is expired. So before executing
the HALT instruction, users have to keep in mind to store the current input port statuses into port
registers.
If the IC is waked-up from the Halt mode by external reset signal, it goes into the reset procedure.
Note: There is a limitation about PH Counter under Halt and Slow mode. Users have to disable
PH counter ($ONOFF[2]) before getting into Halt/Slow Mode.