NXP Semiconductors T2080RDB-PC, User Manual, Page: 43 / 47

3.1.11 Boot configuration override register (BOOTOR)
Address: 0h base + 16h offset = 16h
Bit 0 1 2 3 4 5 6 7
Read
Reserved BOOT_OR
Write
Reset
BOOTOR field descriptions
Field Description
0–6
-
This field is reserved.
7
BOOT_OR
0: Boot configuration from CPLD override disable
1: Boot configuration from CPLD override enable
3.1.12 Boot configuration register 1 (BOOTCFG1 )
Address: 0h base + 17h offset = 17h
Bit 0 1 2 3 4 5 6 7
Read
cfg_rcw_src[0:7]
Write
Reset
BOOTCFG1 field descriptions
Field Description
0–7
cfg_rcw_src[0:7] NOTE: For details, see T2080 Integrated Multicore Communications Processor Family Reference
Manual (document T2080RM).
3.1.13 Boot configuration register 2 (BOOTCFG2)
Address: 0h base + 18h offset = 18h
Bit 0 1 2 3 4 5 6 7
Read
cfg_rcw_
src8
Reserved cfg_svr[0:1] Reserved cfg_eng_use[0:2]
Write
Reset
Chapter 3 CPLD Specification
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 0, 04/2016
Freescale Semiconductor, Inc. 43