• CPLD
• Manages system power and reset sequencing
• Configures DUT, board, clock with dynamic
• Reset and interrupt monitor and control
• General fault monitoring and logging
• Clocks
• System and DDR clock (SYSCLK, DDRCLK)
• Switch selectable to one of the 16 common settings in the interval 64
MHz-166 MHz
• Software programmable in 1 MHz increments from 1-200 MHz
• SerDes clocks
• Provides clocks to all SerDes blocks and slots
• 100 MHz
• 156.25 MHz
• Power supplies
• Dedicated PMBus regulator for core power; adjustable from 0.7 V to 1.3 V at 60
A
• USB
• Supports two USB 2.0 ports with integrated PHYs: Two type A ports with 5 V
@ 1.5 A per port
• MicroSD card
• MicroSD port connects directly to MicroSD or TF
• SPI
• Onboard support of SPI flash
• Other I/O
• Two serial ports
• Two I2C ports
1.5 Block diagram
The T2080RDB-PC supports two modes of operation, the Standalone mode and the
Endpoint mode. There is one configuration in the Standalone mode and second
configurations is in the Endpoint mode, the major differences are in the PCIe support. All
configurations have Freescale C293, 4x XFI, 2x RGMII, DDR, NOR, NAND, SPI
EEPROM, I2C EEPROM, and GPIO. Muxing is controlled by FPGA/CPLD.
Chapter 1 Overview
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 0, 04/2016
Freescale Semiconductor, Inc.
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