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BOOTCFG2 field descriptions

Field

Description

0

cfg_rcw_src8

RCW source bit 8.

1

-

This field is reserved.

2–3

cfg_svr[0:1]

cfg_svr bits for Power-on Reset using.

4

-

This field is reserved.

5–7

cfg_eng_use[0:2]

cfg_eng_use bits for Power-on Reset using.

CPLD Memory Map

QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 0, 04/2016

44

Freescale Semiconductor, Inc.

Summary of Contents for T2080RDB-PC

Page 1: ...QorIQ T2080 Reference Design Board T2080RDB PC User Guide Document Number T2080RDBPCUG Rev 0 04 2016...

Page 2: ...QorIQ T2080 Reference Design Board T2080RDB PC User Guide Rev 0 04 2016 2 Freescale Semiconductor Inc...

Page 3: ...4 Clocks 16 2 5 DDR 17 2 6 SerDes port 18 2 6 1 PCI Express support 20 2 6 2 XFI 10G optics port support 20 2 6 3 XFI 10GBase T port support 21 2 6 4 SATA support 21 2 7 Ethernet controllers 21 2 8 Et...

Page 4: ...4 Software version register SWVER 39 3 1 5 Reset control register RSTCON 39 3 1 6 Flash control and status register FLHCSR 40 3 1 7 Thermal control and status register THMCSR 40 3 1 8 Panel LED contro...

Page 5: ...essor series silicon 1 1 Related documentation The table below lists the related documentation Table 1 1 Related documentation Document name Description T2080 QorIQ Integrated Multicore Communication...

Page 6: ...ernet Controllers ECC Error Detection and Correction EMI Ethernet Management Interfaces eSDHC enhanced Secure Digital Host Controller eSPI enhanced Serial Peripheral Interface FPGA Field Programmable...

Page 7: ...etch engine Data Path Acceleration Architecture DPAA incorporating acceleration for the following functions Packet parsing classification and distribution Frame Manager 1 1 Queue management for schedu...

Page 8: ...s connections 16 lanes configuration SerDes 1 Lane A B to two 10GSFP MAC9 and MAC10 SerDes 1 Lane C D to two 10GBase T MAC1 and MAC2 SerDes 1 Lane E H to PCIe slot PCIe4 x4 Gen3 SerDes 2 Lane A D to P...

Page 9: ...ports two USB 2 0 ports with integrated PHYs Two type A ports with 5 V 1 5 A per port MicroSD card MicroSD port connects directly to MicroSD or TF SPI Onboard support of SPI flash Other I O Two serial...

Page 10: ...al access management unit FMan Parse classify distribute Buffer HiGig DCB 8 lanes up to 10 GHz SerDes PCle SATA2 0 Perf Monitor Watch point cross trigger Aurora Real time debug 32 KB I Cache 32 KB D C...

Page 11: ...GP11TFIV10 128MB CPLD EPM570G PCA9546 Address 0x77 I2C2_PEX4S NOT USE I2C2_SFP2 I2C2_SFP1 RESET Interrupt Power on conf Other control Address 0x08 Address 0x6A Address 0x88 I2C_1 Address 0x40 Address...

Page 12: ...Block diagram QorIQ T2080 Reference Design Board T2080RDB PC User Guide Rev 0 04 2016 12 Freescale Semiconductor Inc...

Page 13: ...rs Headers Jumper Push buttons and LEDs Temperature DIP switch definition 2 1 Processor The T2080RDB PC supports many features of the T2080 processor as detailed in the following sections 2 2 Power Th...

Page 14: ...ounting holes are provided of sufficient size to allow onboard supplies to be replaced by bench supplies All power supplies can be sequenced as per hardware specifications The power supplies provided...

Page 15: ...Hz X5 C293 Sys_refclk P13PCIE3212 U23 Micro SD Card 12 SPI FLASH U13 N25Q512A13G PCA9516 U22 12V 3V3 VTT VREF PCIEX4 SLOT J20 DDR3_SODIM_ECC 1V35 2V5 3V3 5A 5V0 2A 0V67 4A 0V78 4A 1V2 2A 5V0H For IR34...

Page 16: ..._N C293 C290 Reset Logic T2080 Reset Source select RST_CTL DDR_RSTN NOR FLASH NOR_RSTN PEX4S_RST PEX SLOT EDC_RST_N CS4315 DVI_RST_N 10GBASET PHY AQ1202 EC1_RST_N RGMII GE PHY1 Soft reset register RST...

Page 17: ...33 33MHz SYSCLK 66 66MHz T2080 SD1_REFCLK1_P N SD1_REFCLK2_P N SD2_REFCLK1_P N SD2_REFCLK2_P N P E X S L O T C293 SD1_REFCLK2_P N 100MHz PEX_CLK_P N 100MHz IDT9FGV0641 SD2_REFCLK1_P N 100MHz C290_SYSC...

Page 18: ...S 0 8 DDR_MDM 0 8 DDR_MBA 0 2 DDR_MDOT 0 1 DDR_MAPAR_OUT DDR_MPAR_ERR DDR_MCS 0 3 DDR_MCK_P 0 1 _P N DDR_CAS DDR_RAS DDR_WE DDR_MCKE 0 1 IV35 DDR_RST_N CPLD I2C1_SCL I2C1_SDA MV_REF VTT IV35 SPD_ADDR...

Page 19: ...re supported on the T2080RDB is shown in the table below Table 2 1 SerDes protocols SERDES1 SRDS_PRTCL_S1 A B C D E F G H Per lane PLL mapping 66 XFI9 XFI10 XFI1 XFI2 PCIe4 1111 2222 SERDES2 SRDS_PRTC...

Page 20: ...ution of T2080RDB PC 2 6 1 PCI Express support The T2080RDB PC supports PCIe x4 Gen 3 for golden finger and PCIe x4 Gen 2 for slot 2 6 2 XFI 10G optics port support The T2080 supports evaluation of th...

Page 21: ...J46 MDI Magnetics RJ46 Figure 2 7 XFI interface 2 6 4 SATA support SATA is evaluated using the two onboard SATA headers by selecting a SATA supporting SerDes protocol 2 7 Ethernet controllers The T208...

Page 22: ...t Interface The T2080 has two Ethernet Management Interfaces EMI both powered by LVDD However EMI2 is only used with XFI based PHYs which uses 1 2 V pull up EMI1 is used with all other non XFI based P...

Page 23: ...resources equally available to both local and remote systems The T2080RDB PC uses I2C1 port to access onboard devices such as DDR3 DIMM RTC I2C EEPROM clock generator thermal sensor ADT7481 and core p...

Page 24: ...Channel 2 PCA9546 Channel 1 Channel 0 I2C_ADDR 0X77 T2080 I2C1_SDA I2C2_SFP1_SDA I2C2_SFP2_SCL I2C2_SFP2_SDA I2C2_CHAN2_SCL I2C2_CHAN2_SDA I2C2_PEX4S_SCL I2C2_PEX4S_SDA I2C_ADDR 0x4C I2C_ADDR 0x50 I2...

Page 25: ...Control TXBN0304 1 8V 3 3V CPLD Cfg_vbank 0 2 IFC_A5 A7 XORs IFC_VA5 7 NOR_CS NOR FLASH JS28F00AM29EWHA NAND_CS NAND FLASH MT29F8G08ABABA WP 3 3V Figure 2 11 IFC bus 2 12 SDHC interface The enhanced...

Page 26: ...are High speed 480 Mbit s full speed 12 Mbit s and low speed 1 5 Mbit s operation Host mode Dual stacked Type A connection The USB ports connect to a standard Type A connector USB1 and USB2 for compat...

Page 27: ...f imp USB Type A INSTALLED Host mode default 5Vz 18 2K 51 1K 18 2K 51 1K MIC2506YM Figure 2 13 USB connectivity implementation 2 14 RS 232 The T2080 processor has two UART controllers which provides a...

Page 28: ...3232 C1 1 C1 3 C2 4 C2 5 GND 15 R1 IN 13 R1 OUT 12 R2 IN 8 R2 OUT 9 T1 IN 11 T1 OUT 14 T2 IN 10 T2 OUT 7 V 2 V 6 VCC 16 FB6 BLM18BD601SN1 R640 4 7K FB9 BLM18BD601SN1 C101 470pF R641 4 7K R174 100 C95...

Page 29: ...rallel port or RS 232 A typical setup using a USB port emulator is shown in the image below Figure 2 15 USB port emulator setup The 16 pin generic header connector carries the COP JTAG signals and the...

Page 30: ...and JTAG COP connector 10 NC Not connected 11 SRESET Routed to the RESET PLD SRESET to the processor is generated from the PLD 12 GND Connected to guard 13 HRESET Routed to the RESET PLD HRESET to the...

Page 31: ...signators Used for Notes J24 Altera Header Used for programming the Altera CPLD devices J26 IR36021 Header Used for programming the IR36021 J3 COP JTAG Used for debugging the T2080 2 16 3 Jumper The t...

Page 32: ...the T2080RDB PC platform Table 2 7 Push buttons on T2080RDB PC platform Reference designators Used for Notes SW5 Reset Used for resetting the whole board SW4 Power on off Used for turning the power on...

Page 33: ...81 measures the ambient board temperature The ADT7481 temperature warning and alarm signals are connected to the CPLD for monitoring CPLD uses these signals to adjust CPU FAN speed and protect the CPU...

Page 34: ...tion is done through switches Table 2 9 POR configuration through switches Switch Signal name Pin name Signal meaning Setting SW1 1 8 cfg_rcw_src 0 7 IFC_AD 8 15 Reset Configuration word source For de...

Page 35: ...3 5 7 CFG_VBANK 0 2 NOR flash bank select 000 bank0 100 bank4 See note2 SW3 8 TEST_SEL_N TEST_SEL_B 1 T2080 1 For SW3 4 BOOT_FLASH_SEL it can act as boot flash selection when BOOT_FLASH_SEL 1 NOR flas...

Page 36: ...DIP switch definition QorIQ T2080 Reference Design Board T2080RDB PC User Guide Rev 0 04 2016 36 Freescale Semiconductor Inc...

Page 37: ...l control and status register THMCSR 8 R W See section 3 1 7 40 13 Panel LED control and status register LEDCSR 8 R W See section 3 1 8 41 14 SFP control and status register SFPCSR 8 R W See section 3...

Page 38: ...ions Field Description 0 7 CHIPID2 0xaa Identification of the CPLD image 3 1 3 Hardware version register HWVER Hardware version register Address 0h base 2h offset 2h Bit 0 1 2 3 4 5 6 7 Read HW_VER Wr...

Page 39: ...iting logic 1 will produce C293 Coprocessor reset signal this bit can auto clear 2 This field is reserved 3 EC1_RST 0 No reset occurs 1 Writing logic 1 will produce RGMII PHY1 RTL82111E VB reset signa...

Page 40: ...W_BANK_SEL1 0 NOR flash bank select bit1 of switch status is 0 1 NOR flash bank select bit1 of switch status is 1 4 SW_BANK_SEL2 0 NOR flash bank select bit2 of switch status is 0 1 NOR flash bank sel...

Page 41: ...register LEDCSR Address 0h base 13h offset 13h Bit 0 1 2 3 4 5 6 7 Read STS_LED Reserved Write Reset 0 0 0 0 0 0 0 0 LEDCSR field descriptions Field Description 0 STS_LED 0 Panel STATUS LED on 1 Pane...

Page 42: ...me SFP used as RXSD 7 SFP2_TXFAIL 0 SFP 2 TX FAIL not occurs 1 SFP 2 TX FAIL occurs 3 1 10 Miscellanies control and status register MISCCSR Address 0h base 15h offset 15h Bit 0 1 2 3 4 5 6 7 Read RUN_...

Page 43: ...s 0h base 17h offset 17h Bit 0 1 2 3 4 5 6 7 Read cfg_rcw_src 0 7 Write Reset BOOTCFG1 field descriptions Field Description 0 7 cfg_rcw_src 0 7 NOTE For details see T2080 Integrated Multicore Communic...

Page 44: ...his field is reserved 2 3 cfg_svr 0 1 cfg_svr bits for Power on Reset using 4 This field is reserved 5 7 cfg_eng_use 0 2 cfg_eng_use bits for Power on Reset using CPLD Memory Map QorIQ T2080 Reference...

Page 45: ...es revisions to this document Table A 1 Revision history Revision Date Topic cross reference Change description Rev 0 06 2015 Initial public release QorIQ T2080 Reference Design Board T2080RDB PC User...

Page 46: ...QorIQ T2080 Reference Design Board T2080RDB PC User Guide Rev 0 04 2016 46 Freescale Semiconductor Inc...

Page 47: ...l parameters that may be provided in Freescale data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including...

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