NXP Semiconductors
JN-RM-2079
QN9090 module development reference manual
JN-RM-2079
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© NXP Semiconductors N.V. 2020. All rights reserved.
Reference manual
Rev. 1.0
— 17 Jan 2020
7 of 31
the following figure; this includes via locations as well. Deviation from these parameters
can cause performance degradation.
Fig 3. Critical Layout of die flag area
Fig 3 shows the critical areas of the device die flag. These are the following:
• Ground vias and locations
• RF output and ground traces
• Die flag shape
4.2 PCB Stack-Up
Complexity is the main factor that will determine whether the design of an application
board can be two-layer, four-layer, or more. From an RF point of view a 4 layers PCB
is preferred to a two layers PCB. Nevertheless, in a very simple application it should
be possible to use a 2 layers PCB.
The recommended board stack-up for either a four-layer or two-layer board design is
as follows:
•
4-layer stack-up:
—
Top: RF routing of transmission lines
—
L2: RF reference ground
—
L3: DC power
—
Bottom: signal routing
•
Two-layer stack-up:
—
Top: RF routing of transmission lines, signals, and ground
—
Bottom: RF reference ground, signal routing, and general ground
RFIO
GND vias
Die flag
