NXP Semiconductors P89LPC952 User Manual Download Page 12 | Manualshive

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Table 2.

Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR
addr.

Bit functions and addresses

Reset value

MSB

LSB

Hex

Binary

Bit address

E7

E6

E5

E4

E3

E2

E1

E0

ACC*

Accumulator

E0H

00

0000 0000

AD0CON

ADC0 control
register

97H

ENBI0

ENADCI0

TMM0

EDGE0

ADCI0

ENADC0

ADCS01

ADCS00

00

0000 0000

AD0INS

ADC0 input
select

A3H

ADI07

ADI06

ADI05

ADI04

ADI03

ADI02

ADI01

ADI00

00

0000 0000

AD0MODA

ADC0 mode
register A

C0H

BNDI0

BURST0

SCC0

SCAN0

-

-

-

-

00

0000 0000

AD0MODB

ADC0 mode
register B

A1H

CLK2

CLK1

CLK0

-

-

-

-

-

00

000x 0000

AUXR1

Auxiliary
function
register

A2H

CLKLP

EBRR

ENT1

ENT0

SRST

0

-

DPS

00

0000 00x0

Bit address

F7

F6

F5

F4

F3

F2

F1

F0

B*

B register

F0H

00

0000 0000

BRGR0_0

Baud rate
generator 0
rate low

BEH

00

0000 0000

BRGR1_0

Baud rate
generator 0
rate high

BFH

00

0000 0000

BRGCON_0 Baud rate

generator 0
control

BDH

-

-

-

-

-

-

SBRGS_0

BRGEN_0 00

xxxx xx00

CMP1

Comparator 1
control register

ACH

-

-

CE1

CP1

CN1

OE1

CO1

CMF1

xx00 0000

CMP2

Comparator 2
control register

ADH

-

-

CE2

CP2

CN2

OE2

CO2

CMF2

xx00 0000

DIVM

CPU clock
divide-by-M
control

95H

00

0000 0000

DPTR

Data pointer
(2 bytes)

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Summary of Contents for P89LPC952

Page 1: ...UM10147 P89LPC952 954 User manual Rev 02 28 April 2008 User manual Document information Info Content Keywords P89LPC952 P89LPC954 Abstract Technical information for the P89LPC952 954 devices ...

Page 2: ...ormation For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NXP Semiconductors UM10147 P89LPC952 954 User manual Revision history Rev Date Description 02 20080428 Added LQFP48 package information 01 20070917 Initial version ...

Page 3: ...XD0 P0 6 CMP1 KBI6 P1 0 TXD0 VDD P3 1 XTAL1 P0 7 T1 KBI7 P3 0 XTAL2 CLKOUT P2 2 MOSI VDD P2 3 MISO P5 7 P2 4 SS P5 6 P2 5 SPICLK P5 5 P4 0 P5 4 P4 1 TRIG P5 3 P1 4 INT1 P5 2 P1 5 RST P5 1 P1 6 P5 0 V SS V SS P1 7 AD04 P4 7 TCLK P2 0 AD07 P4 6 P2 1 AD06 P4 5 TDI P0 0 CMP2 KBI0 AD05 P4 4 P0 1 CIN2B KBI1 AD00 P4 3 RXD1 P0 2 CIN2A KBI2 AD01 P4 2 TXD1 P0 3 CIN1B KBI3 AD02 002aab307 7 8 9 10 11 12 13 14...

Page 4: ... 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 P1 3 INT0 SDA P1 2 T0 SCL P1 1 RXD0 P1 0 TXD0 P3 1 XTAL1 P3 0 XTAL2 CLKOUT VDD P5 7 P5 6 P5 5 P5 4 P1 4 INT1 P1 5 RST P1 6 V SS P1 7 AD04 P2 0 AD07 P2 1 AD06 P0 0 CMP2 KBI0 AD05 P0 1 CIN2B KBI1 AD00 P0 2 CIN2A KBI2 AD01 P0 3 CIN1B KBI3 AD02 P0 4 CIN1A KBI4 AD03 P0 5 CMPREF KBI5 P0 6 CMP1 KBI6 VDD P0 7 T1 KBI7 P2 2 MOSI P2 3 MISO P2 4 SS P2 5 S...

Page 5: ...INT1 P1 5 RST P1 6 V SS P1 7 AD04 P2 0 AD07 P2 1 AD06 P0 0 CMP2 KBI0 AD05 P0 1 CIN2B KBI1 AD00 P0 2 CIN2A KBI2 AD01 P0 3 CIN1B KBI3 AD02 Table 1 Pin description Symbol Pin Type Description LQFP48 PLCC44 LQFP44 P0 0 to P0 7 I O Port 0 Port 0 is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled ...

Page 6: ... 31 I O P0 6 Port 0 bit 6 O CMP1 Comparator 1 output I KBI6 Keyboard input 6 P0 7 T1 KBI7 31 35 29 I O P0 7 Port 0 bit 7 I O T1 Timer counter 1 external count input or overflow output I KBI7 Keyboard input 7 P1 0 to P1 7 I O I 1 Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for three pins as noted below During reset Port 1 latches are configured in the input only m...

Page 7: ...tor frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until VDD has reached its specified level When system power is removed VDD will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required ...

Page 8: ...ial functions as described below P3 0 XTAL2 CLKOUT 7 12 6 I O P3 0 Port 3 bit 0 O XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the flash configuration O CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 ar...

Page 9: ...he internal pull up disabled The operation of Port 5 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations All pins have Schmitt triggered inputs Port 5 also provides various special functions as described below P5 0 16 21 15 I O P5 0 Port 5 bit 0 High current output P5 1 15 20 14 I O P5 1 Port 5 b...

Page 10: ...RABLE OSCILLATOR ON CHIP RC OSCILLATOR WITH CLOCK DOUBLER internal bus CRYSTAL OR RESONATOR POWER MONITOR POWER ON RESET BROWNOUT RESET 002aab305 UART0 ANALOG COMPARATORS 256 BYTE AUXILIARY RAM I2C BUS PORT 3 CONFIGURABLE I Os DEBUGGER INTERFACE P89LPC952 954 WATCHDOG TIMER AND OSCILLATOR TIMER 0 TIMER 1 REAL TIME CLOCK SYSTEM TIMER SPI ADC0 P3 1 0 P2 5 0 1 P2 7 0 2 PORT 4 CONFIGURABLE I Os PORT 5...

Page 11: ...ny SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 wh...

Page 12: ...E2 E1 E0 ACC Accumulator E0H 00 0000 0000 AD0CON ADC0 control register 97H ENBI0 ENADCI0 TMM0 EDGE0 ADCI0 ENADC0 ADCS01 ADCS00 00 0000 0000 AD0INS ADC0 input select A3H ADI07 ADI06 ADI05 ADI04 ADI03 ADI02 ADI01 ADI00 00 0000 0000 AD0MODA ADC0 mode register A C0H BNDI0 BURST0 SCC0 SCAN0 00 0000 0000 AD0MODB ADC0 mode register B A1H CLK2 CLK1 CLK0 00 000x 0000 AUXR1 Auxiliary function register A2H C...

Page 13: ...0000 0000 FMCON Program flash control Read E4H BUSY HVA HVE SV OI 70 0111 0000 Program flash control Write E4H FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 FMDATA Program flash data E5H 00 0000 0000 I2ADR I2C bus slave address register DBH I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 0000 0000 Bit address DF DE DD DC DB DA D9 D8 I2CON I2C bus control register D8...

Page 14: ...upt priority 0 B8H PWDRT PBO PS PSR PT1 PX1 PT0 PX0 00 1 x000 0000 IP0H Interrupt priority 0 high B7H PWDRTH PBOH PSH PSRH PT1H PX1H PT0H PX0H 00 1 x000 0000 Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PST PSPI PC PKBI PI2C 00 1 00x0 0000 IP1H Interrupt priority 1 high F7H PSTH PSPIH PCH PKBIH PI2CH 00 1 00x0 0000 IP2 Interrupt priority 2 D6H PEST1 PES1 PESR1 PADC 00 1 00x0 00...

Page 15: ...P0M2 2 P0M2 1 P0M2 0 00 1 0000 0000 P1M1 Port 1 output mode 1 91H P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3 1 11x1 xx11 P1M2 Port 1 output mode 2 92H P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00 1 00x0 xx00 P2M1 Port 2 output mode 1 A4H P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 P2M1 0 FF 1 1111 1111 P2M2 Port 2 output mode 2 A5H P2M2 5 P2M2 4 P2M2 3 P2M2 2 P2M2 1 P2M2 0 00 1 0000 0000 P3...

Page 16: ...0BUF Serial Port data buffer register 99H xx xxxx xxxx Bit address 9F 9E 9D 9C 9B 9A 99 98 S0CON Serial port control 98H SM0_0 FE _0 SM1_00 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00 0000 0000 S0STAT Serial port extended status register BAH DBMOD_0 INTLO_0 CIDIS_0 DBISEL_0 FE_0 BR_0 OE_0 STINT_0 00 0000 0000 SP Stack pointer 81H 07 0000 0111 SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA S...

Page 17: ... reset the value is 1110 01x1 i e PRE2 to PRE0 are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF 5 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 The only reset source that affects these SFRs is power ...

Page 18: ...ster 0 right LSB FFFEH AD0DAT0 7 0 00 0000 0000 AD0DAT0L ADC0 data register 0 left MSB FFFFH AD0DAT0 9 2 00 0000 0000 AD0DAT1R ADC0 data register 1 right LSB FFFCH AD0DAT1 7 0 00 0000 0000 AD0DAT1L ADC0 data register 1 left MSB FFFDH AD0DAT1 9 2 00 0000 0000 AD0DAT2R ADC0 data register 2 right LSB FFFAH AD0DAT2 7 0 00 0000 0000 AD0DAT2L ADC0 data register 2 left MSB FFFBH AD0DAT2 9 2 00 0000 0000 ...

Page 19: ...predictable AD0DAT7L ADC0 data register 7 left MSB FFF1H AD0DAT7 9 2 BNDSTA0 ADC0 boundary status register FFEDH BRGCON_1 Baud rate generator 1 control FFB3H SBRGS_ 1 BRGEN_ 1 00 2 xxxx xx00 BRG0_1 Baud rate generator 1 rate low FFB4H BRG1_1 Baud rate generator 1 rate high FFB5H FREEZE Peripheral clock freeze FFD0H RTC_F WDT_F T1_F T0_F 00 xxx0 0000 P4M1 Port 4 output mode 1 FFB8H P4M1 7 P4M1 6 P4...

Page 20: ...implemented on chip The P89LPC952 954 has 256 bytes of on chip XDATA memory CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC952 954 has 8 kB 16 kB of on chip Code memory Fig 5 P89LPC952 memory map P89LPC954 is similar 002aaa948 0000h 03FFh 0400h 07FFh 0800h 0BFFh 0C00h 0FFFh SECTOR 0 SECTOR 1 SECTOR 2 SECTOR 3 1000h 13FFh 1400h 17FFh 180...

Page 21: ...pplications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC952 954 is based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC952 954 in order to reduce component count board space and syste...

Page 22: ... configured when the FLASH is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz 2 2 2 Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 1...

Page 23: ...sed to clear or set bit 6 of the TRIM register 2 4 On chip RC oscillator option The P89LPC952 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 at room temperature Note the initial value is better than 1 please refer to the P89LPC952 954...

Page 24: ...t frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode Table 6 On chip RC oscillator trim register TRIM address 96h bit description Bit Symbo...

Page 25: ...requency crystal or high frequency crystal 1 A series resistor may be required to limit crystal drive levels This is especially important for low frequency crystals see text Fig 6 Using the crystal oscillator 002aad364 P89LPC952 954 XTAL1 XTAL2 quartz crystal or ceramic resonator 1 Note The oscillator must be configured in one of the following modes Low frequency crystal medium frequency crystal o...

Page 26: ...nged by the program at any time without interrupting code execution 2 9 Low power select The P89LPC952 954 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MHz or ...

Page 27: ... will be generated after the conversion completes The input channel is selected in the ADINS register This mode is selected by setting the SCAN0 bit in the ADMODA register 3 2 1 2 Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the eight result register pairs see Table 8 The user...

Page 28: ... result register pair which corresponds to the selected input channel See Table 7 The user may select whether an interrupt if enabled will be generated after either the first four conversions have occurred or all selected channels have been converted If the user selects to generate an interrupt after the four input channels have been converted a second interrupt will be generated after the remaini...

Page 29: ... to the selected input channel See Table 7 May be used with any of the start modes This mode is selected by clearing the BURST0 SCC0 and SCAN0 bits in the ADMODA register 3 2 2 Conversion mode selection bits The A D uses three bits in ADMODA to select the conversion mode These mode bits are summarized in Table 10 below Combinations of the three bits other than the combinations shown are undefined ...

Page 30: ...n Timer triggered mode Prior to resuming conversions the user will need to reset the input multiplexer to the first user specified channel This can be accomplished by writing the ADINS register with the desired channels 3 2 5 Boundary limits interrupt The A D converter has both a high and low boundary limit register The user may select whether an interrupt is generated when the conversion result i...

Page 31: ...or Total Power down mode the A D does not function If the A D is enabled it will consume power Power can be reduced by disabling the A D Table 11 A D Control register 0 ADCON0 address 97h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENBI0 ENADCI0 TMM0 EDGE0 ADCI0 ENADC0 ADCS01 ADCS00 Reset 0 0 0 0 0 0 0 0 Table 12 A D Control register 0 ADCON0 address 97h bit description Bit Symbol Description 1 0 AD...

Page 32: ...0 0 0 0 Table 16 A D Mode register B ADMODB address A1h bit description Bit Symbol Description 0 FCIIS Four conversion intermediate interrupt select When 1 will generate an interrupt after four conversions in fixed channel or dual channel continuous modes In any of the scan modes setting this bit will generate an interrupt after the fourth conversion if the number of channels selected is greater t...

Page 33: ...eset 0 0 0 0 0 0 0 0 Table 20 Boundary status register 0 BNDSTA0 address FFEDh bit description Bit Symbol Description 0 BST00 When set indicates that conversion result for the AD00 pin was inside outside the boundary limits This bit is cleared in software by writing a 1 to this bit 1 BST01 When set indicates that conversion result for the AD01 pin was inside outside the boundary limits This bit is...

Page 34: ...down mode 4 1 Interrupt priority structure There are four SFRs associated with the four interrupt levels IP0 IP0H IP1 IP1H Every interrupt has two bits in IPx and IPxH x 0 1 and can therefore be assigned to one of four levels as shown in Table 22 The P89LPC952 954 has two external interrupt inputs in addition to the Keypad Interrupt function The two interrupt inputs are identical to those present ...

Page 35: ...he glitch suppression circuits Therefore INT1 has glitch suppression while INT0 does not Table 22 Summary of interrupts Description Interrupt flag bit s Vector address Interrupt enable bit s Interrupt priority Arbitration ranking Power down wake up External interrupt 0 IE0 0003h EX0 IEN0 0 IP0H 0 IP0 0 1 highest Yes Timer 0 interrupt TF0 000Bh ET0 IEN0 1 IP0H 1 IP0 1 4 No External interrupt 1 IE1 ...

Page 36: ... reset options chosen see Table 23 Fig 9 Interrupt sources interrupt enables and power down wake up sources 002aab408 IE0 EX0 IE1 EX1 BOF EBO KBIF EKBI interrupt to CPU wake up if in power down EWDRT CMF2 CMF1 EC EA IE0 7 TF1 ET1 TI_0 and RI_0 RI_0 ES ESR TI_0 EST SI EI2C SPIF ESPI RTCF ERTC RTCCON 1 WDOVF TF0 ET0 TI_1 and RI_1 RI_1 1 ES1 ESR1 TI_1 EADC EST1 ENADCI0 ADCI0 ENBI0 BNDI0 Table 23 Numb...

Page 37: ...l output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a lo...

Page 38: ...scouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC952 954 data sheet Dynamic characteristics for glitch filter specifications 5 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port pin when the port latch contains a l...

Page 39: ... has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 13 A push pull port pin has a Schmitt triggered input that also has a glitch suppress...

Page 40: ...tal inputs disabled will be read as 0 by any instruction that accesses the port On any reset PT0AD bits 1 through 5 default to logic 0s to enable the digital functions 5 7 Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices After power up all I O pins except P1 5 may be configured by software Pin P1 5 is input...

Page 41: ... T1 P1 0 P1M1 0 P1M2 0 TXD P1 1 P1M1 1 P1M2 1 RXD P1 2 P1M1 2 P1M2 2 T0 SCL Input only or open drain P1 3 P1M1 3 P1M2 3 INTO SDA input only or open drain P1 4 P1M1 4 P1M2 4 INT1 P1 5 P1M1 5 P1M2 5 RST P1 6 P1M1 6 P1M2 6 OCB P1 7 P1M1 7 P1M2 7 OCC AD04 P2 0 P2M1 0 P2M2 0 ICB AD07 P2 1 P2M1 1 P2M2 1 OCD AD06 P2 2 P2M1 2 P2M2 2 MOSI P2 3 P2M1 3 P2M2 3 MISO P2 4 P2M1 4 P2M2 4 SS P2 5 P2M1 5 P2M2 5 SPI...

Page 42: ...e disabled or enabled PMOD1 PMOD0 is used to select the power reduction mode If PMOD1 PMOD0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption BOPD defaults to logic 0 indicating brownout detection is enabled on power on if BOE is programmed If Brownout Detection is enabled the brownout condition occurs when VDD falls below the Brownout trip voltage VBO see P89LPC...

Page 43: ...PMOD1 PMOD0 PCON 1 0 BOPD PCON 5 BOI PCON 4 EBO IEN0 5 EA IEN0 7 Description 0 erased XX X X X X Brownout disabled VDD operating range is 2 4 V to 3 6 V 1 program med 11 total power down X X X X 11 any mode other than total power down 1 brownout detect power down X X X Brownout disabled VDD operating range is 2 4 V to 3 6 V However BOPD is default to logic 0 upon power up 0 brownout detect active ...

Page 44: ...l start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 256 clocks after start up for the internal RC or external clock input configurations Some chip functions continue to operate and draw power during Power down mode increasing th...

Page 45: ...CON is accessed as SM0 for the UART When logic 1 bit 7 of SCON is accessed as the framing error status FE for the UART 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 10 Table 30 Powe...

Page 46: ... 5 must be enabled An external circuit is required to hold the device in reset at power up until VDD has reached its specified level When system power is removed VDD will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when VDD falls below the mini...

Page 47: ...Description 0 R_EX external reset Flag When this bit is logic 1 it indicates external pin reset Cleared by software by writing a logic 0 to the bit or a Power on reset If RST is still asserted after the Power on reset is over R_EX will be set 1 R_SF software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset 2 R_WD Watchdog Timer reset flag Cleared by software by wr...

Page 48: ...ich the transition was detected Since it takes two machine cycles four CPU clocks to recognize a 1 to 0 transition the maximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle The Timer or Counter func...

Page 49: ...ed when the TR1 control bit is set Table 36 Timer Counter Mode register TMOD address 89h bit description continued Bit Symbol Description Table 37 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1M2 T0M2 Reset x x x 0 x x x 0 Table 38 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit description Bit Symbol Description 0 T0M2 Mode Select ...

Page 50: ...it counters The logic for Mode 3 on Timer 0 is shown in Figure 18 TL0 uses the Timer 0 control bits T0C T T0GATE TR0 INT0 and TF0 TH0 is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus TH0 now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC952 954 devic...

Page 51: ...when external interrupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software 4 TR0 Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off 5 TF0 Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in mode 6 where it is cleared in hardware...

Page 52: ...in Mode 2 8 bit auto reload 002aaa921 PCLK Tn pin TRn Gate INTn pin C T 0 C T 1 TLn 8 bits THn 8 bits TFn control ENTn Tn pin toggle overflow interrupt reload Fig 18 Timer counter 0 Mode 3 two 8 bit counters 002aaa922 PCLK Osc 2 T0 pin TR0 TR1 Gate INT0 pin C T 0 C T 1 TL0 8 bits TF0 control ENT0 AUXR1 4 T0 pin P1 2 open drain toggle overflow interrupt TH0 8 bits TF1 control ENT1 AUXR1 5 T1 pin P0...

Page 53: ...lator is used as the CPU clock then the RTC will use CCLK as its clock source regardless of the state of the RTCS1 0 in the RTCCON register There are three SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload high bits 22 to 15 RTCL Real time Clock counter reload low bits 14 to 7 The Real time clock system timer can be enabled by setting the RTCEN RTCCON 0 bit T...

Page 54: ...red before updating RTCS1 RTCS0 9 3 Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IEN0 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device 9 4 Reset sources affecting the Real time clock Only power on reset will reset the Real time Clock and its associated SFRs ...

Page 55: ...oscillator 100 0 00 High frequency crystal Watchdog oscillator DIVM 01 Medium frequency crystal 10 Low frequency crystal 11 Watchdog oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 101 x xx undefined undefined 110 x xx undefined undefined 111 0 00 External clock input External clock input DIVM 01 10 1...

Page 56: ...Register SnCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection on page 57 10 3 Mode 2 11 bits are transmitted through TXDn or received through RXDn start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 When data is transmitted the 9th data bit TB8 in SnCON can...

Page 57: ...e The UART SFRs are at the following locations 10 6 Baud Rate generator and selection The P89LPC952 954 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1_n and BRGR0_n SFRs Each UART can use either Timer 1 or the baud rate generator output as determined by BRGCON_n 2 1 see Figure 21 Note that Timer T1 is further divided by 2 if th...

Page 58: ...Baud Rate Generator Control register BRGCON_0 address BDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SBRGS_0 BRGEN_0 Reset x x x x x x 0 0 Table 47 Baud Rate Generator Control register BRGCON address BDh bit description Bit Symbol Description 0 BRGEN _0 Baud Rate Generator 0 Enable Enables the baud rate generator BRGR1_0 and BRGR0_0 can only be written when BRGEN_0 0 1 SBRGS _0 Select Baud Rate Gen...

Page 59: ...rate generation for UARTs Modes 1 3 baud rate modes 1 and 3 SBRGS 1 SBRGS 0 SMOD1 0 SMOD1 1 timer 1 overflow PCLK based baud rate generator CCLK based 002aaa897 2 Table 50 Serial Port 0 Control register S0CON address 98h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SM0_0 F E_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 Reset x x x x x x 0 0 Table 51 Serial Port 0 Control register S0CON address 98h bit d...

Page 60: ...9th data bit bit 8 If SMOD0 1 it is set near the middle of the stop bit see SM2_1 S1CON 5 for exceptions Must be cleared by software 1 TI_1 Transmit interrupt flag 1 Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO_1 bit in S1STAT register in the other modes Must be cleared by software 2 RB8_1 The 9th data bit that was received in Modes 2 and 3 I...

Page 61: ... see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL _0 Double buffering transmit interrupt select 0 Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to S0BUF and there is also one more transmit interrupt generated at the...

Page 62: ...software 4 DBISEL _1 Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to S1BUF and there is also one more transmit interrupt generated at the beginning INTLO_1 0 or the end INTLO_1 1 of the STOP bit o...

Page 63: ...e accepted during the first bit time is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SnBUF and RB8_n and to set RI_n will be generated if and only if t...

Page 64: ...9th data bit goes into RB_n and the first 8 data bits go into SnBUF 10 13 Framing error and RI_n in Modes 2 and 3 with SM2_n 1 If SM2_n 1 in modes 2 and 3 RI_n and FE_n behaves as in the following table Fig 23 Serial Port Mode 1 only single transmit buffering case is shown transmit start bit stop bit INTLO 0 TX clock write to SBUF shift TXD TI D0 D1 D5 D2 D6 D3 D4 D7 receive RX clock shift RI star...

Page 65: ...fering can be disabled If disabled DBMOD_n i e SnSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out 10 16 Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD_n 0 10 17 Transmit interrupts with doub...

Page 66: ...Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO_n is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Go to 3 10 18 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD_n i e SnSTAT 7 0 TB8_n can be written before or after Sn...

Page 67: ...the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL_n is logic 1 and the CPU is writing to SnBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following 10 19 Mu...

Page 68: ...se of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme In the above example SnADDR is the same and the SnADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 wo...

Page 69: ...ism to suspend and resume serial transfer The I2C bus may be used for test and diagnostic purposes A typical I2C bus configuration is shown in Figure 26 Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number...

Page 70: ...ta is located at the MSB of I2DAT 11 2 I2C slave address register I2ADR register is readable and writable and is only used when the I2C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized Fig 26 I2C bus configuration OTHER DEVICE WITH I2C BUS INTERFACE SDA SCL Rpu Rpu OTHER DE...

Page 71: ...dition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I2C bus if it is in master mode and transmits a START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus Table 65 I2C Control register I2CON address D8h bit allocation Bit 7 6...

Page 72: ...ndition is transmitted to the I2C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed Slave Receiver Mode The STO flag is cleared by hardware automatical...

Page 73: ...e set to 1 to enable the I2C function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to 0 Table 69 I2C clock rates selection Bit data rate Kbit sec at fosc I2SCLL I2SCLH CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz 6 0 307...

Page 74: ... bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or 0B0h if the slave mode was enabled setting AA Logic 1 The appropriate action to be taken for each of these status codes is shown in Table 72 11 6 2 Master Receiver mode In the Master Receiver Mode data is received from a slave transmitter The transfer started in the sam...

Page 75: ...e data direction bit which is 0 W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 75 for the status codes and actions Fig 28 Format of Master Receiver mode S R A slave address logic 0 write logic 1 read from master to slave...

Page 76: ...quested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I2C bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer Fig 30 Format of Slave Receiver mode S W A sla...

Page 77: ...S 002aaa899 ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 I2ADR ACK BIT COUNTER ARBITRATION AND SYNC LOGIC 8 I2DAT TIMING AND CONTROL LOGIC SERIAL CLOCK GENERATOR CCLK interrupt INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE P1 3 P1 3 SDA P1 2 SCL P1 2 timer 1 overflow CONTROL REGISTERS AND SCL DUTY CYCLE REGISTERS I2CON I2SCLH I2SCLL 8 STATUS DECODER status bus STATUS REGISTER 8 I2STAT ...

Page 78: ...DAT action or 0 1 0 x STOP condition will be transmitted STO flag will be reset no I2DAT action 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W has been transmitted NOT ACK has been received Load data byte or 0 0 0 x Data byte will be transmitted ACK bit will be received no I2DAT action or 1 0 0 x Repeated START will be transmitted no I2DAT...

Page 79: ...eceiver mode Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI STA 08H A START condition has been transmitted Load SLA R x 0 0 x SLA R will be transmitted ACK bit will be received 10H A repeat START condition has been transmitted Load SLA R or x 0 0 x As above Load SLA W SLA W will be transmitted I2C bus ...

Page 80: ...STA STO SI AA 60H Own SLA W has been received ACK has been received no I2DAT action or x 0 0 0 Data byte will be received and NOT ACK will be returned no I2DAT action x 0 0 1 Data byte will be received and ACK will be returned 68H Arbitration lost in SLA R Was master Own SLA W has been received ACK returned No I2DAT action or x 0 0 0 Data byte will be received and NOT ACK will be returned no I2DAT...

Page 81: ...a has been received ACK has been returned Read data byte or x 0 0 0 Data byte will be received and NOT ACK will be returned read data byte x 0 0 1 Data byte will be received and ACK will be returned 98H Previously addressed with General call Data has been received NACK has been returned Read data byte 0 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address read...

Page 82: ...ecomes free Table 74 Slave Receiver mode continued Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI AA Table 75 Slave Transmitter mode Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI AA A8h Own SLA R has been ...

Page 83: ... will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free C8H Last data byte in I2DAT has been transmitted AA 0 ACK has been received No I2DAT action or 0 0 0 0 Switched to not addressed SLA mode no...

Page 84: ...sabled i e SPEN SPCTL 6 0 reset value If the SPI is configured as a master i e MSTR SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits If the SS pin is ignored i e SSIG SPCTL 7 bit 1 this pin is configured for port functions Note that even if the SPI is configured as a master MSTR 1 it can still be converted to a slave by driving the SS pin low if P2 4 is configured a...

Page 85: ...the data word is transmitted first 0 The MSB of the data word is transmitted first 6 SPEN SPI Enable 1 The SPI is enabled 0 The SPI is disabled and all SPI pins will be port pins 7 SSIG SS IGnore 1 MSTR bit 4 decides whether the device is a master or slave 0 The SS pin decides whether the device is master or slave The SS pin can be used as a port pin see Table 81 Table 78 SPI Status register SPSTA...

Page 86: ...nfigured in quasi bidirectional mode When a device initiates a transfer it can configure P2 4 as an output and drive it low forcing a mode change in the other device see Section 12 4 Mode change on SS to slave Table 80 SPI Data register SPDAT address E3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol MSB LSB Reset 0 0 0 0 0 0 0 0 Fig 34 SPI single master single slave configuration Fig 35 SPI dual devic...

Page 87: ...8 BIT SHIFT REGISTER SPI CLOCK GENERATOR 8 BIT SHIFT REGISTER MISO MOSI SPICLK port port MISO MOSI SPICLK SS slave 8 BIT SHIFT REGISTER MISO MOSI SPICLK SS Table 81 SPI master and slave selection SPEN SSIG SS Pin MSTR Master or Slave Mode MISO MOSI SPICLK Remarks 0 x P2 4 1 x SPI Disabled P2 3 1 P2 2 1 P2 5 1 SPI disabled P2 2 P2 3 P2 4 P2 5 are used as port pins 1 0 0 0 Slave output input input S...

Page 88: ... low Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt is enab...

Page 89: ...et to indicate data collision when the data register is written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for both a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The slave howev...

Page 90: ...M10147 P89LPC952 954 User manual 1 Not defined Fig 37 SPI slave transfer format with CPHA 0 1 2 3 4 5 6 7 8 MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB 1 002aaa934 Clock cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI input MISO output SS if SSIG bit 0 ...

Page 91: ...M10147 P89LPC952 954 User manual 1 Not defined Fig 38 SPI slave transfer format with CPHA 1 1 2 3 4 5 6 7 8 MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB 002aaa935 Clock cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI input MISO output SS if SSIG bit 0 1 ...

Page 92: ...UM10147 P89LPC952 954 User manual 1 Not defined Fig 39 SPI master transfer format with CPHA 0 1 2 3 4 5 6 7 8 MSB LSB 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB 002aaa936 Clock cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI input MISO output SS if SSIG bit 0 DORD 0 DORD 1 ...

Page 93: ... or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes 13 1 Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 The control registers are identical and are shown in Table 83 The overall connections to both comparators are shown in Figure 41 The...

Page 94: ...e interrupt if enabled Cleared by software 1 COn Comparator output synchronized to the CPU clock to allow reading by software 2 OEn Output enable When logic 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This output is asynchronous to the CPU clock 3 CNn Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected as the neg...

Page 95: ...is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user shou...

Page 96: ...n CIN1A Negative input from CMPREF pin Output to CMP1 pin enabled CALL delay10us The comparator needs at least 10 microseconds before use ANL CMP1 0FEh Clear comparator 1 interrupt flag SETB EC Enable the comparator interrupt SETB EA Enable the interrupt system if needed RET Return to caller The interrupt routine used for the comparator must clear the interrupt flag CMF1 in this case before return...

Page 97: ... then any key connected to Port0 which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order...

Page 98: ...the WDT Following reset this bit will be set and the WDT will be running All writes to WDCON need to be followed by a feed sequence see Section 15 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the WDT can be used in timer mode and be enabled to produce an interrupt IEN0 6 if desired ...

Page 99: ...sor was in Power down mode the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable 15 2 Feed sequence The watchdog timer control register and the 8 bit down counter See Figure 44 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the con...

Page 100: ...is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WDCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a watchd...

Page 101: ...mer Time Out Flag This bit is set when the 8 bit down counter underflows In watchdog mode a feed sequence will clear this bit It can also be cleared by writing a logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to 1 watchdog running and cannot be cleared to zero if both WDTE and WDSE are set to 1 3 4...

Page 102: ...caler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles Note When switching clocks it is important that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the watchdog may become disabled when the old clock source is...

Page 103: ...n underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode Fig 44 Watchdog Timer in Watchdog Mode WDTE 1 PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK WDCON A7H SHADOW REGISTER PRESCALER 002aaa905 8 BI...

Page 104: ...r contains several special purpose control bits that relate to several chip features AUXR1 is described in Table 95 Table 94 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENT0 SRST 0 DPS Reset 0 0 0 0 0 0 x 0 Table 95 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not used Allowab...

Page 105: ...VX A DPTR Move accumulator to data memory relative to DPTR MOVX DPTR A Move from data memory relative to DPTR to the accumulator Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC952 954 since the part does not have an external dat...

Page 106: ...ption Bit Symbol Description 0 T0_F Timer 0 Freeze bit When set the clock to Timer 0 will be frozen while performing monitor operations in debugger mode 1 T1_F Timer 1Freeze bit When set the clock to Timer 1 will be frozen while performing monitor operations in debugger mode 2 WDT_F Watchdog timer Freeze bit When set the clock to the Watchdog timer will be frozen while performing monitor operation...

Page 107: ...plication in addition to IAP Lite Default serial loader providing In System Programming ISP via the serial port located in upper end of user program memory Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space providing flexibility to the user Programming and erase over the full operating voltage range Read Programming Erase using ISP IAP IAP Lite ICP and ...

Page 108: ...ritten the value written to FMDATA will be stored in the page register at the location specified by the lower 6 bits of FMADRL In addition the update flag for that location will be set FMADRL will auto increment to the next location Auto increment after writing to the last byte in the page register will wrap around to the first byte in the page register but will not affect FMADRL 7 6 Bytes loaded ...

Page 109: ... byte in the page register Write the address of the next byte to be programmed to FMADRL if desired Not needed for contiguous bytes since FMADRL is auto incremented All bytes to be programmed must be within the same page Write the data for the next byte to be programmed to FMDATA Repeat writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register Write the page a...

Page 110: ...R0 A get pointer into R0 LOAD_PAGE MOV FMDAT R0 write data to page register INC R0 point to next byte DJNZ R3 LOAD_PAGE do until count is zero MOV FMCON EP else erase program the page MOV R7 FMCON copy status for return MOV A R7 read status ANL A 0FH save only four lower bits JNZ BAD CLR C clear error flag if good 3 HVA R High voltage abort Set if either an interrupt or a brown out is detected dur...

Page 111: ...page_lo write my page address to addr regs for i 0 i 64 i i 1 FMDATA dbytes i FMCON EP erase prog page command Fm_stat FMCON read the result status if Fm_stat 0x0F 0 prog_fail 1 else prog_fail 0 return prog_fail 17 5 In circuit programming ICP In Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the...

Page 112: ...pace This function is in addition to the IAP Lite feature 17 8 Power on reset code execution The P89LPC952 954 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC952 954 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s appl...

Page 113: ...lity consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC952 954 through the serial port This firmware is provided by NXP and embedded within each P89LPC952 954 device The NXP In System Programming facility has made in circuit programming in an embedded application possible with a minimum of additional expense in componen...

Page 114: ...l record types will be added to indicate either commands or data for the ISP facility The maximum number of data bytes in a record is limited to 64 decimal ISP commands are summarized in Table 102 As a record is received by the P89LPC952 954 the information in the record is stored internally and a checksum calculation is performed The operation indicated by the record type is not performed until t...

Page 115: ...00000001cc 02 Miscellaneous Write Functions 02xxxx02ssddcc Where xxxx required field but value is a don t care ss subfunction code dd data cc checksum Subfunction codes 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 0E Security Byte 6 0F...

Page 116: ...7 10 Manufacturer Id 11 Device Id 12 Derivative Id 18 Security Byte 8 89LPC954 19 Security Byte 9 89LPC954 1A Security Byte 10 89LPC954 1B Security Byte 11 89LPC954 1C Security Byte 12 89LPC954 1D Security Byte 13 89LPC954 1E Security Byte 14 89LPC954 1F Security Byte 15 89LPC954 Example 0100000312cc 04 Erase Sector Page 03xxxx04ssaaaacc Where xxxx required field but value is a don t care aaaa sec...

Page 117: ... call After the function call is processed by the IAP routine the authorization key will be cleared Thus it is necessary for the authorization key to be set prior to EACH call to PGM_MTP that requires a key If an IAP routine that requires an authorization key is called without a valid authorization key present the MCU will perform a reset 17 14 Flash write enable This device has hardware write ena...

Page 118: ...amming the BOOTSTAT register This bit is cleared by using the Clear Configuration Protection CCP command in IAP or ISP The Clear Configuration Protection command can be disabled in ISP or IAP mode by programming the Disable Clear Configuration Protection bit DCCP in BOOTSTAT 7 to a logic 1 When DCCP is set the CCP command may still be used in ICP or parallel programming modes This bit is cleared b...

Page 119: ...ty settings Cycle is aborted Memory contents are unchanged CRC output is invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may be corrupted 3 VE Verify error Set during IAP programming of user code if the contents of the programmed address does not agree with the intended programmed value IAP uses the MOVC instruction to per...

Page 120: ...s ACC 01h Return parameter s R7 IAP version id Misc Write requires key Input parameters ACC 02h R5 data to write R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 0E Security Byte 6 0F Security Byte 7 10 Clear Configuration Protection 18 Security Byt...

Page 121: ...er Id 11 Device Id 12 Derivative Id 18 Security Byte 8 89LPC954 19 Security Byte 9 89LPC954 1A Security Byte 10 89LPC954 1B Security Byte 11 89LPC954 1C Security Byte 12 89LPC954 1D Security Byte 13 89LPC954 1E Security Byte 14 89LPC954 1F Security Byte 15 89LPC954 Return parameter s R7 register data if no error else error status Carry set on error clear on no error Erase Sector Page requires key ...

Page 122: ...06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read User Code Input parameters ACC 07h R4 address MSB R5 address LSB Return parameter s R7 data Table 104 IAP function calls continued IAP function IAP call parameters Table 105 Flash User Configuration Byte 1 UCFG1 bit allocation Bi...

Page 123: ... the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 90 Watchdog timer configuration for details Table 106 Flash User Configuration Byte 1 UCFG1 bit description continued Bit Symbol Description Table 107 Oscillator type selection FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 20 30 tolerance 011 Internal ...

Page 124: ...ial programmer This bit and sector x CANNOT be erased in ISP or IAP modes 3 7 reserved Table 112 Effects of Security Bits EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Pr...

Page 125: ... internal flag can be set or cleared using the Set Write Enable SWE or Clear Write Enable CWE commands 6 CWP Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 BOOTVEC and BOOTSTAT If programmed to a logic 1 the writes to these registers are disabled If programmed to a logic 0 writes to these registers are enabled This bit is set by progr...

Page 126: ...w 1 1 96 to 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 to 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 to 07 DEC A Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data pointer 1 ...

Page 127: ... Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 to 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 to F7 MOV Ri dir Move direct byte to indirect memory 2 2...

Page 128: ...2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 1...

Page 129: ...cluding without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure ...

Page 130: ...ble 33 Reset Sources register RSTSRC address DFh bit allocation 47 Table 34 Reset Sources register RSTSRC address DFh bit description 47 Table 35 Timer Counter Mode register TMOD address 89h bit allocation 48 Table 36 Timer Counter Mode register TMOD address 89h bit description 48 Table 37 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation 49 Table 38 Timer Counter Auxiliary Mo...

Page 131: ...pt Mask register KBMASK address 86h bit allocation 98 Table 89 Keypad Interrupt Mask register KBMASK address 86h bit description 98 Table 90 Watchdog timer configuration 99 Table 91 Watchdog Timer Control register WDCON address A7h bit allocation 101 Table 92 Watchdog Timer Control register WDCON address A7h bit description 101 Table 93 Watchdog timeout vales 101 Table 94 AUXR1 register address A2...

Page 132: ... buffering must be disabled 63 Fig 23 Serial Port Mode 1 only single transmit buffering case is shown 64 Fig 24 Serial Port Mode 2 or 3 only single transmit buffering case is shown 64 Fig 25 Transmission with and without double buffering 66 Fig 26 I2C bus configuration 70 Fig 27 Format in the Master Transmitter mode 74 Fig 28 Format of Master Receiver mode 75 Fig 29 A Master Receiver switches to M...

Page 133: ...nfiguration 37 5 3 Open drain output configuration 38 5 4 Input only configuration 39 5 5 Push pull output configuration 39 5 6 Port 0 and Analog Comparator functions 40 5 7 Additional port features 40 6 Power monitoring functions 42 6 1 Brownout detection 42 6 2 Power on detection 43 6 3 Power reduction modes 43 7 Reset 46 7 1 Reset vector 48 8 Timers 0 and 1 48 8 1 Mode 0 49 8 2 Mode 1 50 8 3 Mo...

Page 134: ...tchdog Timer in Timer mode 103 15 5 Power down operation 104 15 6 Periodic wake up from power down without an external oscillator 104 16 Additional features 104 16 1 Software reset 105 16 2 Dual Data Pointers 105 16 3 Debugger interface 105 16 3 1 Debugger connections 106 17 Flash memory 107 17 1 General description 107 17 2 Features 107 17 3 Flash programming and erase 107 17 4 Using Flash as dat...

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