NXP Semiconductors LS1046ARDB, Reference Manual, Page: 53 / 64

Diagram
Bits 0 1 2 3 4 5 6 7
R
SD1REFC... Reserved
W
Reset SW4[5] 0000000
Fields
Field Function
0
SD1REFCLK_S
EL
SD1REFCLK_SEL
SerDes1 reference clock 2 setting register
0: 100 MHz
1: 156.25 MHz (default value)
1-7
-
Reserved
3.12 Ethernet Controller 2 Connection Control Register (REG_
RGMII_1588_SEL)
Offset
Register Offset
REG_RGMII_1588_SEL Bh
Function
Use this register to configure ethernet controller 2 connection.
Ethernet Controller 2 Connection Control Register (REG_RGMII_1588_SEL)
QorIQ LS1046A Reference Design Board Reference Manual, Rev. 2, 30 May 2019
NXP Semiconductors
53