NXP Semiconductors LS1046ARDB, Reference Manual, Page: 43 / 64

3.1 CPLD Major Revision Register (CPLD_VER)
Offset
Register Offset
CPLD_VER 0h
Function
Read this register to get CPLD major revision.
Diagram
Bits
0 1 2 3 4 5 6 7
R CPLD_VER
Reserved
W
Reset 1000 0000
Fields
Field Function
0-3
CPLD_VER
CPLD_VER
CPLD major revision number
4-7
-
Reserved
3.2 CPLD Minor Revision Register (CPLD_VER_SUB)
Offset
Register Offset
CPLD_VER_SUB 1h
Function
Read this register to get CPLD minor revision.
CPLD Major Revision Register (CPLD_VER)
QorIQ LS1046A Reference Design Board Reference Manual, Rev. 2, 30 May 2019
NXP Semiconductors
43