Table 3. LS1046ARDB features (continued)
Board feature
Processor feature used
Description
DDR
One 32-/64-bit DDR4 SDRAM
memory controller with ECC
• Supports data rates of up to 2100 MT/s
• Supports 64-bit data bus
• Supports an onboard dual-rank, 8 GB, x72 unbuffered
DDR4 memory module (eight data byte lanes + ECC) on
a DDR4 DIMM socket
• Supports double-bit error detection and single-bit error
correction ECC (8-bit check word across 64-bit data)
• Supports four chip selects
SerDes
Two SerDes modules (SerDes1 and
SerDes2), each having four lanes
with speeds of up to 10 Gbit/s
SerDes1:
• Lane 0: Supports an AQR107 PHY, provides a 10.3125
GbE port
• Lane 1: Supports an XFI retimer, provides an SFP+ cage
• Lane 2: Supports an SGMII PHY, provides a 1.25 GbE
port
• Lane 3: Supports an SGMII PHY, provides a 1.25 GbE
port
SerDes2:
• Lane 0: Supports a mini-PCIe x1 (Gen 1/2/3) slot for a
Wi-Fi module
• Lane 1: Supports a PCIe x1 (Gen 1/2/3) slot for a PCIe
x1 card
• Lane 2: Supports a PCIe x1 (Gen 1/2/3) slot for a PCIe
x1 card
• Lane 3: Supports a SATA 3.0 connector for a SATA 3.0
drive
The LS1046ARDB does not support
PCIe Gen 3 and SATA at the same time.
NOTE
Ethernet
Two Ethernet controllers (EC1 and
EC2)
• Supports two RGMII PHYs, provides two 1G/100M/10M
Ethernet ports through a 1x2 RJ45 connector
EMI
Two Ethernet management interfaces
(EMI1 and EMI2)
• EMI1: Controls SGMII and RGMII PHYs
• EMI2: Controls AQR107 PHY
USB 3.0
Three USB 3.0 controllers (USB1,
USB2, and USB3) with integrated
PHYs
• USB1: Supports a USB 3.0 Type A connector configured
in the Host mode, by default
• USB2: Supports a USB 3.0 micro-AB connector
configured in the On-The-Go (OTG) mode, by default
• USB3: Connects to the mini-PCIe slot
Table continues on the next page...
LS1046ARDB Overview
QorIQ LS1046A Reference Design Board Reference Manual, Rev. 2, 30 May 2019
10
NXP Semiconductors