2.1 Secure GPIO Mask
Each GPIO has a Secure GPIO MASK. As shown in
Fig 4
, we can think of the Secure GPIO Mask as one input of the AND gate.
Its default value is 1. Through Secure GPIO Mask, we can control the on/off state of the normal GPIO read path.
2.2 Secure GPIO
As shown in
Fig 4
, Secure GPIO has the same functions as normal GPIO. However, the access rules to this Secure GPIO for
different secure levels are configured through the Secure AHB controller which can only be accessed in Secure state.
2.3 Secure PINT
The main difference between Secure PINT and PINT is that the Secure PINT only supports up to two pins on Port 0. Similar as
Secure GPIO, the access rules to this module are configured through the Secure AHB controller.
The Secure Pin Interrupt Generator and the Secure Pattern Match Engine are available on all LPC55S6x devices.
Similar as normal PINT, the Secure Pin Interrupt Generator, and the Secure Pattern Match Engine are mutually exclusive.
2.3.1 Secure Pin Interrupts
– For Secure PINT block, up to two pins can be selected from all pins on port 0 , as edge-sensitive or level-sensitive interrupt
requests. Each request creates a separate interrupt in the NVIC.
– Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.
– Level-sensitive interrupt pins can be HIGH-active or LOW-active.
2.3.2 Secure Pattern Match Engine
– Up to
two pins can be selected from all digital pins on port 0 to contribute to a boolean expression. The boolean expression
consists of specified levels and/or transitions on various combinations of these pins.
– Each bit slice minterm (product term) comprising the specified boolean expression can generate its own, dedicated interrupt
request.
– Any occurrence of a pattern match can be programmed to generate an RXEV notification to the CPU.
– Pattern match can be used in conjunction with software, to create complex state machines based on pin inputs.
3 Usage
3.1 Use Secure GPIO Mask to protect Secure digital peripherals which need IO
SEC_GPIO_MASK register is used for controlling Secure GPIO Mask. Default register value is all 1, which means NS code can
still read Secure peripheral states by reading its pin states as shown in left side of
Fig 5
below.
To prevent this risk of secure information leakage, the normal GPIO shall be masked by setting the corresponding bits in
SEC_GPIO_MASK to 0, as shown in the right side of
Fig 5
below.
NXP Semiconductors
Usage
LPC55S6x Secure GPIO and Usage, Rev. 0, 15 January 2019
Application Note
6 / 12
