Figure 3. Normal GPIO
2 Secure GPIO, Secure GPIO Mask and Secure PINT
Due to the architecture of normal GPIO, all digital IO pins states are readable through normal GPIO module from the GPIO read
path, independent of which function is chosen for this pin as aforementioned. As a result, there is a possibility of leaking information
from secure resource(S).
For example, when a UART is configured as a Secure peripheral, which means that this UART is only allowed to be accessed by
the Secure-world (i.e. code), not by the Non-secure world.
However, in this case, the UART pin states can still be monitored by Non-secure world through normal GPIO read path as shown
in
Fig 3
. Hence, the Non-secure world can get all the Secure UART’s information.
To solve this issue and safeguard incoming data on Secure peripherals, Secure GPIO Mask is implemented on LPC55S6x.
NXP Semiconductors
Secure GPIO, Secure GPIO Mask and Secure PINT
LPC55S6x Secure GPIO and Usage, Rev. 0, 15 January 2019
Application Note
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