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NXP Semiconductors

JN-RM-2080

K32W module development reference manual

JN-RM-2080

All information provided in this document is subject to legal disclaimers.

© NXP Semiconductors N.V. 2020. All rights reserved.

Reference manual

Rev. 1.0

— 27 Mar 2020

16 of 30

Contact information

For more information, please visit:

http://www.nxp.com

C

1

3

C

14

V

D

D

(Ra

d

io

)

Fig 12. VDD(Radio) decoupling

Fig 13. FB and VDD_PMU decoupling

C100

V

D

D

E

Fig 14. VDDE decoupling

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Summary of Contents for K32W

Page 1: ...RM 2080 K32W module development reference manual Rev 1 0 27 Mar 2020 Reference manual Document information Info Content Keywords K32W061 041 module Abstract Reference Manual for K32W061 041 modules a...

Page 2: ...All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2020 All rights reserved Reference manual Rev 1 0 27 Mar 2020 2 of 30 Contact information For more info...

Page 3: ...o 640 kB flash 152 kB SRAM and 128 kB ROM BLE Link layer processing hardware and peripherals optimized to meet the requirements of the target applications The design considerations presented in this m...

Page 4: ...r each module variant Reference manual JN RM 2080 Schematics Layout Bill of Materials Full design databases including schematics and layout source files are available on request The following table pr...

Page 5: ...ss hardware development the proper device footprint RF layout circuit matching antenna design and RF measurement capability are essential RF circuit design layout and antenna design are specialties re...

Page 6: ...M13 DCDC external components 32 kHz XTAL 32 MHz XTAL RFIO MatchingNetwork IF Printed antenna Fl connector FEM SKY66403 Fig 4 K32W061 001 M16 The device footprint and layout are critical as the RF per...

Page 7: ...he critical RF section which must be copied exactly for optimal radio performance The less critical layout area can be modified without reducing radio performance NOTE Exact dimensions are not given i...

Page 8: ...r either a four layer or two layer board design is as follows 4 layer stack up Top RF routing of transmission lines L2 RF reference ground L3 DC power Bottom signal routing Two layer stack up Top RF r...

Page 9: ...n boards in which the bare PCB s were all fabricated in the same lot However when the product goes into mass production there can be variations in PCB fabrication from lot to lot which can degrade per...

Page 10: ...ectric constant of the board material trace width and the board thickness between the trace and the ground Additionally for CPW the transmission line is defined by the gap between the trace and the to...

Page 11: ...way Typically these effects become worse as the frequency of operation is increased For most component suppliers this quality is expressed by the Self Resonant Frequency SRF specification For example...

Page 12: ...designs It is certainly possible to substitute another vendor s parts but it may impact the performance of the circuit therefore it may be necessary to use different component values when parts from a...

Page 13: ...ically for a 1 6mm thickness PCB material a single via can add 1 2nH of inductance and 0 5pF of capacitance depending upon the via dimensions and PCB dielectric material Provide multiple vias for high...

Page 14: ...ible offset specified in BLE 5 specification is 50 ppm and 40ppm in the IEE802 15 4 spec Also note that this tolerance should include both temperature and ageing effects imparted on the resonator Reso...

Page 15: ...ias The viasare too far fromthe decouplingcapacitors Fig 10 GND vias placement The capacitor with a smaller capacitance must be placed nearer to the IC The decoupling capacitor must be placed between...

Page 16: ...n this document is subject to legal disclaimers NXP Semiconductors N V 2020 All rights reserved Reference manual Rev 1 0 27 Mar 2020 16 of 30 Contact information For more information please visit http...

Page 17: ...as RF trace oscillator power lines and separate them from any signal that is likely to couple with them through parasitics Separation between 2 lines can be achieved by increasing the distance from on...

Page 18: ...for all layers of the PCB and not just the top layer Any conductive objects close to the antenna could severely disrupt the antenna pattern resulting in deep nulls and high directivity in some directi...

Page 19: ...1 mm for the smaller pads and a 6 4 mm square pad for the paddle Warning Solder resist area recommended Fig 17 Recommended PCB decal for HVQFN40 40 pin QFN The solder mask used is shown in Fig 19 The...

Page 20: ...f 30 Contact information For more information please visit http www nxp com Fig 19 Solder paste mask for HVQFN40 40 pin QFN Fig 20 Vias on the paddle of the HVQFN40 40 pin QFN 25 vias are applied to t...

Page 21: ...icle 10 8 of the Radio Equipment Directive 2014 53 EU a Frequency bands in which the equipment operates b The maximum RF power transmitted PN RF Technology a Freq Ranges EU b Max Transmitted Power K32...

Page 22: ...g components that had not previously used for such applications 1 4 Have the non standard components been qualified so that they can be used in the application 1 5 Are recommendations for layout form...

Page 23: ...TAL model has not been recommended by NXP have all the parameters been checked in order they fulfill NXP standard and application requirements load capacitance pulling sensitivity equivalent resistanc...

Page 24: ...utput from the pin for sensitivity measurements 8 5 For printed and chip antenna Is the RF line implemented in such a way that the HW can be easily modified in order to do conducted measurements on on...

Page 25: ...followed 1 4 Has the correct PCB material been specified 1 5 Have the correct PCB thicknesses been specified 2 RF IO 2 1 Is the RF_IO input output line well sized for 50 ohm The line width must be ca...

Page 26: ...are used does one layer act as a continuous ground plane GND reference plane 5 2 Are numerous vias added near capacitor near fingers 5 3 Remove small GND areas and isolated fingers that cannot be con...

Page 27: ...0 10 Abbreviations Table 4 Abbreviations Acronym Description EMC Electro Magnetic Compatibility ETSI European Telecommunications Standards Institute FCC Federal Communications Commission PAN Personal...

Page 28: ...cal Layout of die flag area 7 Fig 6 PCB stack up 8 Fig 7 RF Matching Network 11 Fig 8 RF Plots for 3pF ceramic capacitor Murata GRM1555 type 12 Fig 9 GND path between C10 C12 and C19 13 Fig 10 GND via...

Page 29: ...tion provided in this document is subject to legal disclaimers NXP Semiconductors N V 2020 All rights reserved Reference manual Rev 1 0 27 Mar 2020 29 of 30 13 List of tables Table 1 Modules reference...

Page 30: ...4 3 Block diagram 5 4 Design considerations 5 4 1 K32W061 041 device footprint 7 4 2 PCB Stack Up 8 4 3 RF circuit topology and matching 9 4 4 Transmission lines 10 4 5 Components 11 4 6 GND planes 12...

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