NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1001 / 1379

PORT memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4005_E0C0 Digital Filter Enable Register (PORTE_DFER) 32 R/W 0000_0000h 38.5.7/1006
4005_E0C4 Digital Filter Clock Register (PORTE_DFCR) 32 R/W 0000_0000h 38.5.8/1007
4005_E0C8 Digital Filter Width Register (PORTE_DFWR) 32 R/W 0000_0000h 38.5.9/1008
38.5.1 Pin Control Register n (PORTx_PCRn)
NOTE
See the GPIO Configuration section for details on the available
functions for each pin.
Do not modify pin configuration registers associated with pins
that are not available in a reduced-pin package offering.
Unbonded pins not available in a package are disabled by
default to prevent them from consuming power.
Address: Base a 0h (4d × i), where i=0d to 31d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 ISF 0
IRQC
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LK
0
MUX
0
DSE ODE PFE
0
SRE PE PS
W
Reset
0 0 0 0 0 * * * 0 * 0 * 0 * * *
* Notes:
MUX field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. •
DSE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. •
PFE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. •
SRE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. •
PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. •
PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. •
PORTx_PCRn field descriptions
Field Description
31–25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 38 Port Control and Interrupts (PORT)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1001