NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1008 / 1379

38.5.9 Digital Filter Width Register (PORTx_DFWR)
This register is read only for ports that do not support a digital filter.
The digital filter configuration is valid in all digital pin muxing modes.
Address: Base a C8h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FILT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_DFWR field descriptions
Field Description
31–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FILT Filter Length
The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the
glitches, in clock cycles, that the digital filter absorbs for the enabled digital filters. Glitches that are longer
than this register setting will pass through the digital filter, and glitches that are equal to or less than this
register setting are filtered. Changing the filter length must be done only after all filters are disabled.
38.6 Functional description
38.6.1 Pin control
Each port pin has a corresponding Pin Control register, PORT_PCRn, associated with it.
The upper half of the Pin Control register configures the pin's capability to either
interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as
well as a logic level occurring on the port pin. It also includes a flag to indicate that an
interrupt has occurred.
The lower half of the Pin Control register configures the following functions for each pin
within the 32-bit port.
• Pullup or pulldown enable on selected pins
• Drive strength and slew rate configuration on selected pins
• Open drain enable on selected pins
• Passive input filter enable on selected pins
• Pin Muxing mode
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1008 NXP Semiconductors