NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1002 / 1379

PORTx_PCRn field descriptions (continued)
Field Description
24
ISF
Interrupt Status Flag
The pin interrupt configuration is valid in all digital pin muxing modes.
0 Configured interrupt is not detected.
1 Configured interrupt is detected. If the pin is configured to generate a DMA request, then the
corresponding flag will be cleared automatically at the completion of the requested DMA transfer.
Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level
sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is
cleared.
23–20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19–16
IRQC
Interrupt Configuration
The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured
to generate interrupt/DMA request as follows:
0000 Interrupt Status Flag (ISF) is disabled.
0001 ISF flag and DMA request on rising edge.
0010 ISF flag and DMA request on falling edge.
0011 ISF flag and DMA request on either edge.
0100 Reserved.
0101 Flag sets on rising edge.
0110 Flag sets on falling edge.
0111 Flag sets on either edge.
1000 ISF flag and Interrupt when logic 0.
1001 ISF flag and Interrupt on rising-edge.
1010 ISF flag and Interrupt on falling-edge.
1011 ISF flag and Interrupt on either edge.
1100 ISF flag and Interrupt when logic 1.
1101 Enable active high trigger output, flag is disabled. [The trigger output goes to the trigger mux,
which allows pins to trigger other peripherals (configurable polarity; 1 pin per port; if multiple pins
are configured, then they are ORed together to create the trigger)]
1110 Enable active low trigger output, flag is disabled.
1111 Reserved.
15
LK
Lock Register
0 Pin Control Register fields [15:0] are not locked.
1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
14–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
MUX Pin Mux Control
Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in
configuring the pin for a different pin muxing slot.
The corresponding pin is configured in the following pin muxing slot as follows:
000 Pin disabled (Alternative 0) (analog).
001 Alternative 1 (GPIO).
010 Alternative 2 (chip-specific).
Table continues on the next page...
Memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1002 NXP Semiconductors