NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Modes of Operation
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor 3-11
3.8.3 Stop4 Mode
Stop4 is differentiated from stop2 and stop3 in that the on-chip regulator is fully engaged.
Entry into halt mode from run mode is enabled if the XCSR[ENBDM] bit is set. This register is described
in
Chapter 20, “Version 1 ColdFire Debug (CF1_DEBUG).” If XCSR[ENBDM] is set when the CPU
executes a STOP instruction, the system clocks to the background debug logic remain active when the
MCU enters stop mode. Because of this, background debug communication remains possible. If you
attempt to enter stop2 or stop3 with XCSR[ENBDM] set, the MCU enters stop4 instead (see
Table 3-2 for
details).
Stop4 is also entered if SPMSC1[LVDE, LVDSE] are set, enabling low voltage detect when the STOP
instruction is executed. The LVD may only be used when the on-chip regulator is in full regulation mode.
Thus, stop3 and stop2 modes are not compatible with use of the LVD.
The LVD system is capable of generating an interrupt or a reset when the supply voltage drops below the
LVD voltage.
Stop4 can be exited by asserting RESET or by an interrupt from one of the following sources: RTC, LVD,
LVW, ADC, IRQ, SCI or KBI.
3.9 On-Chip Peripheral Modules in Stop and Low-Power Modes
When the MCU enters any stop mode (wait not included), system clocks to the internal peripheral modules
are stopped. Even in the exception case (XCSR[ENBDM] = 1), where clocks to the background debug
logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer
to
Section 3.8.1, “Stop2 Mode,” and Section 3.8.2, “Stop3 Mode,” for specific information on system
behavior in stop modes.
When the MCU enters LPwait or LPrun modes, system clocks to the internal peripheral modules continue
based on the settings of the clock gating control registers (SCGC1-4).
Table 3-4 defines terms used in Table 3-5 to describe operation of components on the device in the various
low-power modes.
Table 3-4. Abbreviations used in Table 3-5
Voltage Regulator Clocked
1
1
Subject to module enables and settings of System Clock Gating
Control Registers 1 through 4 (SCGC1-4).
Not Clocked
Full Regulation FullOn FullNoClk
FullADACK
2
2
ADC-specific mode where the device is fully regulated and the
normal peripheral clock is stopped. The ADC can run using its
internally generated asynchronous ADACK clock.
Soft Regulation SoftOn
3
SoftNoClk
Disabled
SoftADACK
4
Off N/A Off