Modes of Operation
MCF51CN128 Reference Manual, Rev. 6
3-10
Freescale Semiconductor
•
The LVD reset function is enabled and the MCU remains in the reset state if V
DD
is below the LVD
trip point (low trip point selected due to POR).
•
The CPU initiates reset exception processing by fetching the vectors at 0x(00)00_0000 and
0x(00)00_0004.
In addition to the above, upon waking up from stop2, SPMSC2[PPDF] is set. This flag is used to direct
user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until
a 1 is written to SPMSC2[PPDACK].
Wakeup from stop2 can be initiated with an RTC interrupt. Unlike most other modules on the device, the
RTC is not reset as a result of exiting stop2. This implies that the RTC interrupt is asserted (although
masked) upon exit from stop2.
To maintain I/O states for pins configured as general-purpose I/O, application software must save their
state in RAM prior to entering stop2. During the routine called after exit from STOP2, software must
restore the contents of the I/O port registers to the port registers before writing to the PPDACK bit. If the
port registers are not restored from RAM, the pins switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, reconfigure the peripheral module that interfaces to the
pin before writing to PPDACK. If the peripheral module is not enabled before writing to PPDACK, the
pins are controlled by their associated port control registers when the I/O latches are opened.
3.8.1.1
Oscillator Considerations for Stop2
If using a low-range oscillator during stop2, reconfigure the MCGC2 register before PPDACK is written.
If the low-range oscillator is active when entering stop2, it remains active in stop2 regardless of the value
of MCGC2[EREFSTEN]. To disable the oscillator in stop2, switch the MCG into FBI or FEI mode before
executing the STOP instruction.
The crystal oscillator cannot be used in high range in Stop2. Systems which use crystals in the high
frequency range (up to 25MHz) must disable the crystal oscillator and switch to FBI or FEI mode prior to
executing the STOP instruction.
3.8.2
Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. The
on-chip regulator is placed in standby state.
Stop3 can be exited by asserting RESET or by an interrupt from one of the following sources: RTC, ADC,
IRQ, SCI, or KBI.
If stop3 is exited by the RESET pin, the MCU is reset and operation resumes after taking the reset vector.
Exit by one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector.
