Modes of Operation
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
3-9
3.8
Stop Modes
One of three stop modes is entered upon execution of a STOP instruction when SOPT1[STOPE] is set and
SOPT1[WAITE] is cleared. In stop3 mode, the bus and CPU clocks are halted. If XCSR[ENBDM] is set
prior to entering stop4, only the peripheral clocks are halted. The MCG module can be configured to leave
the reference clocks running. See
Chapter 6, “Multipurpose Clock Generator (MCG),”
for more
information.
NOTE
If neither the WAITE or STOPE bit is set when the CPU executes a STOP
instruction, the MCU does not enter either of the stop modes. Instead, the
MCU initiates an illegal opcode reset if CPUCR[IRD] is cleared or an
illegal instruction exception if CPUCR[IRD] is set.
The stop modes are selected by setting the appropriate bits in the system power management status and
control 2 (SPMSC2) register.
shows the control bits that affect mode selection under various
conditions. The selected mode is entered following the execution of a STOP instruction.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in stop or wait mode. The
BACKGROUND command can wake the MCU from stop4 and enter halt mode if XCSR[ENBDM] was
set prior to entering stop. After entering halt mode, all background commands are available.
The interrupts that can wake the MPU from stop modes must be masked using the module interrupt enable
functions. For more information, refer to interrupts from any of the following sources: ADC, PMC, IRQ,
KBI, RTC, and SCI.
3.8.1
Stop2 Mode
Stop2 mode is entered by executing a STOP instruction under the conditions as shown in
Most of the internal circuitry of the MCU is powered off in stop2 except for the RAM and optionally the
RTC. After entering stop2, all I/O pin control signals are latched so that the pins retain their states during
stop2.
Exit from stop2 is performed by asserting the wakeup pin (RESET/PTC3) low.
NOTE
RESET/PTC3 functions as an active-low wakeup input when the MCU is in
stop2 if the pin is configured as an input before entering stop2. The pullup
on this pin is not enabled in stop2 unless PTCPE[PTCPE3] is set.
In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.
Upon wakeup from stop2 mode, the MCU resumes as from a power-on reset (POR):
•
All module control and status registers are reset, except the power management controller
(SPMSC1/2/4), RTC, and debug trace buffer. Refer to the individual module chapters for more
information on which other registers are unaffected by wakeup from stop2 mode.
