MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
20-1
Chapter 20
Version 1 ColdFire Debug (CF1_DEBUG)
20.1
Introduction
This chapter describes the capabilities defined by the Version 1 ColdFire debug architecture. The Version 1
ColdFire core supports BDM functionality using the HCS08’s single-pin interface. The traditional 3-pin
full-duplex ColdFire BDM serial communication protocol based on 17-bit data packets is replaced with
the HCS08 debug protocol where all communication is based on an 8-bit data packet using a single
package pin (BKGD).
An on-chip trace buffer allows a stream of compressed processor execution status packets to be recorded
for subsequent retrieval to provide program (and partial data) trace capabilities.
The following sections in this chapter provide details on the BKGD pin, the background debug serial
interface controller (BDC), a standard 6-pin BDM connector, the BDM command set as well as real-time
debug and trace capabilities. The V1 definition supports revision B+ () of the ColdFire debug
architecture.
A simplified block diagram of the V1 core including the processor and debug module is shown in
.
NOTE
Use pin mux control registers from
Section 2.3, “Pin Mux Controls
” to
assign the debug signals to the device’s package pins.
