NXP Semiconductors freescale semiconductor ColdFire MCF51CN128 Series, Reference Manual

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Version 1 ColdFire Debug (CF1_DEBUG)
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor 20-65
20.4.3.4.2 Supervisor Instruction Set
The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown
below. The PST/DDATA specification for these opcodes is shown in
Table 20-28 .
1
During normal exception processing, the PSTB is loaded with two successive 0x1C entries indicating the exception
processing state. The exception stack write operands, as well as the vector read and target address of the exception
handler may also be displayed.
Exception Processing:
PST = 0x1C, 0x1C,
{PST = 0x0B,DD = destination}, // stack frame
{PST = 0x0B,DD = destination}, // stack frame
{PST = 0x0B,DD = source}, // vector read
PST = 0x05,{PST = 0x0[DE],DD = target} // handler PC
A similar set of PST/DD values is generated in response to an emulator mode excetion. For these events (caused
by a debug interrupt or properly-enabled trace exception), the initial PST values are 0x1D, 0x1D and the remaining
sequence is equivalent to normal exception processing.
The PST
/
DDATA specification for the reset exception is shown below:
Exception Processing:
PST = 0x1C, 0x1C,
PST = 0x05,{PST = 0x0[DE],DD = target} // initial PC
The initial references at address 0 and 4 are never captured nor displayed because these accesses are treated as
instruction fetches.
For all types of exception processing, the PST = 0x1C (or 0x1D) value is driven for two trace buffer entries.
2
For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address
fields defining variant
addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi),
(d8,PC,Xi).
Table 20-28. PST/DDATA Specification for Supervisor-Mode Instructions
Instruction Operand Syntax PST/DDATA
halt PST = 0x1F,
PST = 0x1F
move.l Ay,USP PST = 0x01
move.l USP,Ax PST = 0x01
move.w SR,Dx PST = 0x01
move.w {Dy,#<data>},SR PST = 0x01, {PST = 0x03}
movec.l Ry,Rc PST = 0x01
rte PST = 0x07, {PST = 0x0B, DD = source operand}, {PST = 0x03}, {PST = 0x0B,
DD = source operand},
PST = 0x05, {PST = 0x0[DE], DD = target address}
stldsr.w #imm PST = 0x01, {PST = 0x0B, DD = destination operand, PST = 0x03}
stop #<data> PST = 0x1E,
PST = 0x1E
wdebug.l <ea>y PST = 0x01, {PST = 0x0B, DD = source, PST = 0x0B, DD = source}