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NuDAQ ACL-8112 Series, User Manual

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NuDAQ ACL-8112 Series User Manual Download Page 22

14 

•

 Installation 

The ACL-8112 offer 16 single-ended or 8 differential  analog input 
channels. The jumper JP3 controls the analog input channel 
configuration. The setting of JP3 is specified as following illustration. 
 

 

Figure 2.3 Analog Input Channels Configuration 

2.7  DMA Channel Setting 

The A/D data transfer of ACL-8112 is designed with DMA transfer 
capability. The setting of DMA channel 1 or channel 3 is controlled by the 
jumpers JP7 and JP8 of ACL-8112DG/HG, or JP1 and JP2 of ACL-
8112PG . The possible settings are shown below: 

 

Note: On floppy disk only machine, we suggest you to set DMA level 3. If 

you have hard disk equipped computer, level 1 is preferable. 

 

Summary of Contents for ACL-8112 Series

Page 1: ...NuDAQ ACL 8112 Series Enhanced Multi Functions Data Acquisition Cards User s Guide ...

Page 2: ...sing out of the use or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copyright All rights are reserved No part of this manual may be reproduced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Trademarks NuDAQ ACL 8112 are regist...

Page 3: ...NuPRO nupro adlink com tw Software sw adlink com tw AMB amb adlink com tw TEL 886 2 82265877 FAX 886 2 82265717 Address 9F No 166 Jian Yi Road Chungho City Taipei 235 Taiwan R O C Please inform or FAX us of your detailed information for a prompt satisfactory and constant service Detailed Company Information Company Organization Contact Person E mail Address Address Country TEL FAX Web Site Questio...

Page 4: ......

Page 5: ...rnal External Trigger Setting 15 2 9 Clock Source Setting 17 2 10 IRQ Level Setting 17 2 11 D A Reference Voltage Setting 18 2 12 A D Input Range Setting 19 Chapter 3 Signal Connections 20 3 1 Connectors Pin Assignment 20 3 2 Analog Input Signal Connection 22 3 3 Analog Output Signal Connection 24 3 4 Digital I O Connection 25 3 5 Timer Counter Connection 25 3 6 Daughter Board Connection 26 3 6 3 ...

Page 6: ... Modes 40 5 1 3 A D Data Transfer Modes 40 5 2 D A Conversion 42 5 3 Digital Input and Output 43 5 4 Timer Counter Operation 43 Chapter 6 Calibration Utilities 48 6 1 What do you need 48 6 2 VR Assignment 48 6 3 A D Adjustment 49 6 3 1 Bipolar Calibration 49 6 3 2 Unipolar Calibration 49 6 4 D A Adjustment 50 Chapter 7 C Language Library 51 7 1 _8112_Initial 51 7 2 _8112_Switch_Card_No 54 7 3 _811...

Page 7: ..._DMA_Status 74 7 16 _8112_AD_DMA_Stop 74 7 17 _8112_AD_INT_Start 75 7 18 _8112_AD_INT_Status 76 7 19 _8112_AD_INT_Stop 78 7 20 _8112_AD_Timer 78 7 21 _8112_TIMER_Start 79 7 22 _8112_TIMER_Read 81 7 23 _8112_TIMER_Stop 82 Appendix A Demo Programs 83 Product Warranty Service 84 ...

Page 8: ...ter 3 Signal Connection describes the connectors pin assignment and how to connect the outside signal and devices with the ACL 8112 Ø Chapter 4 Registers describes the details of register format and structure of the ACL 8112 this information is very important for the programmers who want to control the hardware by low level programming Ø Chapter 5 Operation Theorem describes how to operate the ACL...

Page 9: ...am of the ACL 8112 The ACL 8112 Series consists of three products the ACL 8112HG ACL 8112DG and ACL 8112PG The ACL 8112HG provides special high gain programmable instrument amplifier for low level input applications such as measure thermocouple signals The ACL 8112DG provides high speed sample rate up to 100 Khz at all gains x1 x2 x4 and x8 The ACL 8112PG provides 16 single ended inputs at up to 1...

Page 10: ... BIT COUNTER 1 16 BIT COUNTER 2 TO PACER TRIG 16 BIT DIGITAL INPUT REGISTER 12 Bit Code Latch 16 channel Single ended or 8 Differential Analog Multiplexer AMP DC DC CONVERTER 15 15 5V MUX SCAN CONTROL 12 Bit Code Latch D A 1 12 BIT MULITIPLYING D A DATA BUFFER INTERRUPT IRQ SELECT CONTROL LOGIC DACK I O PORT DECODER INTERNAL BUS GAIN SELECT D A 0 12 BIT MULITIPLYING D A 12 Bit A D Converter B B 77...

Page 11: ...n chip sample hold Ø Two 12 bit monolithic multiplying analog output channels Ø 16 digital output channels Ø 16 digital input channels Ø 3 programmable 16 bit down counters Ø Programmable sampling rate of up to 100KHz Ø Three A D trigger modes software trigger programmable pacer trigger and external pulse trigger Ø AT interrupt IRQ capability 9 IRQ levels IRQ3 IRQ15 are jumper selectable Ø Integra...

Page 12: ...V 1V 500 mV 100mV 50mV 10mV 5mV Unipolar 0 10V 0 1V 0 0 1V 0 0 01V Ø ACL 8112DG Bipolar 10V 5V 2 5V 1 25V 0 625 Unipolar 0 10V 0 5V 0 2 5V 0 1 25V Ø ACL 8112PG Bipolar 10V 5V 2 5V 1 25V 0 625V Or Bipolar 5V 2 5V 1 25V 0 625V 0 3125V Ø Conversion Time 8 µ sec Ø Overvoltage protection Continuous 35V maximum Ø Accuracy ACL 8112HG GAIN 0 5 1 0 01 of FSR 1 LSB GAIN 5 10 0 02 of FSR 1 LSB GAIN 50 100 0 ...

Page 13: ...DG HG Analog Output D A Ø Converter DAC7541 or equivalent monolithic multiplying Ø Number of channels 2 double buffered analog outputs Ø Resolution 12 bit Ø Output Range Internal reference unipolar 0 5V or 0 10V External reference unipolar max 10V or 10V Ø Settling Time 30 µ sec Ø Linearity 1 2 bit LSB Ø Output driving capability 5mA max Digital I O DIO Ø Number of channels 16 TTL compatible input...

Page 14: ...al clock sourse General Specifications Ø I O Base Address 16 consecutive address location Ø Interrupt IRQ IRQ3 5 6 7 9 10 11 12 15 9 levels Ø DMA Channel CH1 and CH3 Jumper selectable Ø Connector 37 pin D type connector Ø Operating Temperature 0 C 55 C Ø Storage Temperature 20 C 80 C Ø Humidity 5 95 non condensing Ø Power Consumption ACL 8112DG HG 5 V 430 mA typical 12V 150 mA typical ACL 8112PG 5...

Page 15: ...Q ISA Bus Cards with Analog I O windows 3 1 95 98 NT ACLS DLL2 can be used for many programming environments such as VC VB Delphi ACLS DLL2 is included in the ADLINK CD It need license 1 4 2 LabView Driver The ACLS LVIEW includes the ACL 8112 s Vis which is used to interface with NI s LabView software package The ACLS LVIEW supports Windows 95 98 NT ACLS LVIEW is included in the ADLINK CD It need ...

Page 16: ...n addition to this User s Manual the package includes the following items Ø ACL 8112 Enhanced Multi function Data Acquisition Card Ø ADLINK CD If any of these items is missing or damaged contact the dealer from whom you purchased the product Save the shipping materials and carton in case you want to ship or store the product in the future Note The utilities and libraries in CD ROM only support ACL...

Page 17: ...ge Shipping and handling may cause damage to your module Be sure there are no shipping and handing damages on the module before processing After opening the card module carton extract the system module and place it only on a grounded anti static surface component side up Again inspect the module for damage Press down on all the socketed IC s to make sure that they are properly seated Do this only ...

Page 18: ...R1VR2 VR3 VR4 SW1 ADS774 8112 Ver C DACK VR5 CN2 CN1 8254 JP3 JP2 EXT1 EXT2 INT VR7 VR6 DIFF SING DRQ JP1 5V 10V JP4 EXTTRG INTTRG JP6 EXTCLK INTCLK JP7 JP8 3 5 6 7 9 10111215NC JP5 1 3 X 1 3 X Figure 2 1 1 PCB Layout of the ACL 8112DG HG Ver C ...

Page 19: ...VR3 VR4 SW1 ADS774 8112PG Ver B1 DRQ VR5 CN2 CN1 8254 JP7 EXT1 EXT2 INT JP8 5V 10V JP5 EXTTRG INTTRG JP4 EXTCLK INTCLK JP2 JP1 3 5 6 7 910111215X JP3 DC DC Converter DACK 1 2 X 1 2 X JP6 Figure 2 1 2 PCB Layout of the ACL 8112PG ...

Page 20: ...ive address locations in the I O address space The base address of the ACL 8112 is restricted by the following conditions 1 The base address must be within the range Hex 200 to Hex 3FF 2 The base address should not conflict with any PC reserved I O address see Appendix A 3 The base address must not conflict with any add on card on your own PC Please check your PC before installing the ACL 8112 The...

Page 21: ...e Address Combinations How to define the base address for the ACL 8112 The DIP1 to DIP6 in the switch SW1 are one to one corresponding to the PC bus address line A8 to A4 A9 is always 1 and A0 A3 are always 0 If you want to change the base address you can only change the values of A8 to A4 the shadow area of below table The following table is an example which shows you how to define the base addre...

Page 22: ...log Input Channels Configuration 2 7 DMA Channel Setting The A D data transfer of ACL 8112 is designed with DMA transfer capability The setting of DMA channel 1 or channel 3 is controlled by the jumpers JP7 and JP8 of ACL 8112DG HG or JP1 and JP2 of ACL 8112PG The possible settings are shown below Note On floppy disk only machine we suggest you to set DMA level 3 If you have hard disk equipped com...

Page 23: ...rnal or external trigger source is setting by JP4 of ACL 8112DG HG or JP5 of ACL 8112PG as shown on Figure 2 5 Note that there are two internal on board trigger sources one is the software trigger and the other is the programmable pacer trigger which is controlled by the mode control register see section 4 5 Internal Trigger default setting External Trigger JP4 JP5 INTTRG EXTTRG JP4 JP5 INTTRG EXT...

Page 24: ...16 Installation Internal Clock Source 2MHz default setting External Clock Source JP6 JP4 INTCLK EXTCLK JP6 JP4 INTCLK EXTCLK Figure 2 6 Timer s Clock Source Setting ...

Page 25: ...rrupt lines of the PC I O channel The interrupt line is selected by the jumper JP5 of ACL 8112DG HG or JP3 of ACL 8112PG If you wish to use the interrupt capability of ACL 8112 you must select an interrupt level and place the jumper in the appropriate position to enable the particular interrupt line The default interrupt level is IRQ5 which is selected by placing the jumper on the pins in row numb...

Page 26: ...are selected by JP2 of ACL 8112DG HG or JP6 and JP7 of ACL 8112PG respectively Their possible settings are shown as below D A CH1 is External D A CH2 is External JP2 or JP7 JP6 INTREF ExtRef2 ExtRef1 INTREF D A CH1 is External D A CH2 is Internal D A CH1 is Internal D A CH2 is External D A CH1 is Internal D A CH2 is Internal JP2 or JP7 JP6 INTREF ExtRef2 ExtRef1 INTREF JP2 or JP7 JP6 INTREF ExtRef...

Page 27: ... reference voltage is used only when the JP2 of ACL 8112DG HG or JP6 nd JP7 of ACL 8112PG is set to internal reference Reference Voltage is 5V default setting JP1 JP8 10V 5V Reference Voltage is 10V JP1 JP8 10V 5V Figure 2 9 Internal Reference Voltage Setting 2 12 A D Input Range Setting This section is for ACL 8112PG only The A D input range of ACL 8112PG can be set to 5V or 10V by jumper JP9 ...

Page 28: ... and CN2 and one 37 pin D type connector CN3 The CN1 and CN2 are located on board and CN3 located at the rear plate CN2 is used for digital signal input CN1 for digital signal output CN3 for analog input analog output and timer counter s signals The pin assignment for each connectors are illustrated in the Figure 3 1 Figure 3 3 Ø CN2 Digital Signal Input DI 0 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Page 29: ...N1 Legend DO n Digital output signal channel n DI n Digital input signal channel n GND Digital ground Ø CN3 Analog Input Output Counter Timer for single ended connection ACL 8112DG HG PG AI2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 20 31 32 33 34 35 36 37 AI3 AI1 AI0 AI6 AI7 AI5 AI4 A GND A GND V REF ExtRef2 A GND 12V D GND AI10 AI9 AI8 AI13 AI14 AI12 AI11 AO1 ...

Page 30: ...ent of CN3 Legend AIn Analog Input Channel n single ended AIHn Analog High Input Channel n differential AILn Analog Low Input Channel n differential ExtRef n External Reference Voltage for D A CH n AOn Analog Output Channel n ExtCLK External Clock Input ExtTrig External Trigger Signal CLK Clock input for 8254 GATE Gate input for 8254 COUT n Signal output of Counter n V ERF Voltage Reference A GND ...

Page 31: ...n Note that when more than two floating sources are connected the sources must be with common ground Figure 3 4 Floating source and single ended Differential input mode The differential input mode provides two inputs that respond to the difference signal between them If the signal source has one side connected to local ground the differential mode can be used for reducing ground loop Figure 3 5 sh...

Page 32: ... ground of the PC system a shorted ground path must be connected Figure 3 6 shows the connection of differential source Figure 3 6 Differential source and differential input If your signal source is both floating and local ground you should use the differential mode and the floating signal source should be connected as the Figure 3 7 AIHn AILn n 0 8 Floating Signal Source To A D Converter High Low...

Page 33: ...I O Connection The ACL 8112 provides 16 digital input and 16 digital output channels through the connector CN1 and CN2 on board The digital I O signal are fully TTL DTL compatible The detailed digital I O signal specification can be referred in section 1 3 Figure 3 8 Digital I O Connection 3 5 Timer Counter Connection The ACL 8112 has an interval timer counter 8254 on board It offers 3 independent...

Page 34: ... externally and the output is send to the connector CN3 too All the timer counter signals are TTL compatible 3 6 Daughter Board Connection The ACL 8112 can be connected with five different daughter boards ACLD 8125 ACLD 9137 ACLD9182 ACLD9185 and ACLD9188 The functionality and connections are specified as follows 3 6 3 Connect with ACLD 8125 The ACLD 8125 has a 37 pin D sub connector which can con...

Page 35: ...ge of board is an 500Vdc isolation voltage is provided and it can protect your PC system from damage when an abnormal input signal is occurred 3 6 6 Connect with ACLD 9185 The ACLD 9185 is a 16 channel SPDT relay output board This board is connected with CN2 of ACL 8112 via 20 pin flat cable by using this board you can control outside device through the digital output signals 3 6 7 Connect with AC...

Page 36: ...the PC I O address space The Table 4 1 shows the I O address of each register with respect to the base address The function of each register also be shown I O Address Read Write Base 0 Counter 0 Counter 0 Base 1 Counter 1 Counter 1 Base 2 Counter 2 Counter 2 Base 3 Not Used 8254 Counter Control Base 4 A D low byte CH1 D A low byte Base 5 A D high byte CH1 D A high byte Base 6 DI low byte CH2 D A l...

Page 37: ...y Data Format Bit 7 6 5 4 3 2 1 0 BASE 4 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 BASE 5 0 0 0 DRDY AD11 AD10 AD9 AD8 AD11 AD0 Analog to digital data AD11 is the Most Significant Bit MSB AD0 is the Least Significant Bit LSB DRDY Data Ready Signal 1 A D data is not ready 0 A D conversion is completed It will be set to 1 when reading the low byte 4 3 A D Channel Multiplexer Register This register is used to ...

Page 38: ...12PG CS0 and CS1 always be zero CL3 CL0 is used to select the 16 single ended channels Bit Channel 7 X 6 X 5 CS1 4 CS0 3 CL3 2 CL2 1 CL1 0 CL0 S E CH0 X X 0 1 0 0 0 0 S E CH1 X X 0 1 0 0 0 1 S E CH2 X X 0 1 0 0 1 0 S E CH3 X X 0 1 0 0 1 1 S E CH4 X X 0 1 0 1 0 0 S E CH5 X X 0 1 0 1 0 1 S E CH6 X X 0 1 0 1 1 0 S E CH7 X X 0 1 0 1 1 1 S E CH8 X X 1 0 1 0 0 0 S E CH9 X X 1 0 1 0 0 1 S E CH10 X X 1 0 ...

Page 39: ... Table 4 2 shows the relationship between the register data and the A D input range Address BASE 9 Attribute write only Data Format Bit 7 6 5 4 3 2 1 0 BASE 9 X X X X G3 G2 G1 G0 G0 G3 Gain Range selection G3 is not used for ACL 8112PG This table is only for ACL 8112HG High Gain Card G3 G2 G1 G0 GAIN Bipolar or Unipolar Input Range 0 0 0 0 1 Bipolar 5V 0 0 0 1 10 Bipolar 0 5V 0 0 1 0 100 Bipolar 0...

Page 40: ...32 Registers Format 1 1 1 1 1 000 Unipolar N A Table 4 2 1 Function of the Gain Control Bits ...

Page 41: ...the ACL 8112PG the maximum can be changed by hardware jumper setting The jumper JP9 is used to change the maximum analog input range form 5V or 10V If the JP9 is set as 5V the analog input ragne is listed as below G3 G2 G1 G0 GAIN Analog Input Range 0 0 0 0 1 5V 0 0 0 1 2 2 5V 0 0 1 0 4 1 25V 0 0 1 1 8 0 625V 0 1 0 0 16 0 3125V Table 4 2 3 Analog Input Range max is 5V If the JP9 is set as 5V the a...

Page 42: ...er Note 1 When your system power on or reset the A D operation will be initialized as software trigger and program polling mode 2 No matter which mode is selected the external trigger is available if the JP4 is set to be external trigger 3 As long as not the DMA mode is not used the program polling is alwayse possible The syncronization of A D conversion and data transfer should be concerned when ...

Page 43: ... Attribute write only Data Format Bit 7 6 5 4 3 2 1 0 BASE 12 X X X X X X X X 4 8 Digital I O register There are 16 digital input channels and 16 digital output channels are provided by the ACL 8112 The address Base 6 and Base 7 are used for digital input channels and the address Base 13 and Base 14 are used for digital output channels Address BASE 6 BASE 7 Attribute read only Data Format Bit 7 6 ...

Page 44: ...36 Registers Format Base 14 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 ...

Page 45: ...A10 DA9 DA8 DA0 is the LSB and DA11 is the MSB of the 12 bits data X don t care Note The D A registers are double buffered so that the D A analog output signals will not updated until the second high byte is written This can insure a single step transition when the D A conversion 4 10 Internal Timer Counter Register Two counter of 8254 are used for periodically triggering the A D conversion the le...

Page 46: ...38 Registers Format Base 2 Counter 2 Register R W Base 3 8254 CONTROL BYTE ...

Page 47: ...n 5 1 1 A D Conversion Procedure The A D conversion is starting by a trigger source then the A D converter will start to convert the signal to a digital value The ACL 8112 provides three trigger modes see section 5 1 2 While A D conversion the DRDY bit in A D data register is cleared to indicate the data is not ready After conversion being completed the DRDY bit will return to low 0 level It means...

Page 48: ...ervice routine is used to generate a fixed rate trigger Timer Pacer Trigger An on board timer counter chip 8254 is used to provide a trigger source for A D conversion at a fixed rate Two counters of the 8254 chip are cascaded together to generate trigger pulse with precise period Please refer to section 5 4 for 8254 architecture This mode is ideal for high speed A D conversion It can be combined w...

Page 49: ...Operation Theorem 41 mode control register BASE 11 The different transfer modes are specified as follows ...

Page 50: ...tware When the interrupt transfer is used you have to set the interrupt IRQ level by hardware jumper Please refer section 2 10 for IRQ jumper setting After the A D conversion is completed a hardware interrupt will be inserted and its corresponding ISR Interrupt Service Routine will be invoked and executed The converted data is transferred by the ISR program DMA Transfer The DMA Direct Memory Acces...

Page 51: ...ers of the ACL 8112 the low byte must be written before the high byte This procedure can insure a single step transition when the D A conversion 5 3 Digital Input and Output To program digital I O operation is fairly straight forward The digital input operation is just to read data from the corresponding registers and the digital output operation is to write data to the corresponding registers The...

Page 52: ... rate of the ACL 8112 The minimum signal rate is 2MHz 65535 65535 which is a very slow frequency that user may never use it General Purpose Timer Counter The counter 0 is free for users applications The clock source gate control signal and the output signal is send to the connector CN3 The general purpose timer counter can be used as event counter or used for measuring frequency or others function...

Page 53: ... Theorem 45 Control Byte Before loading or reading any of these individual counters the control byte BASE 3 must be loaded first The format of the control byte is Bit 7 6 5 4 3 2 1 0 SC1 SC0 RL1 RL0 M2 M1 M0 BCD ...

Page 54: ... Operating Mode Bit 3 Bit 2 Bit 1 M2 M1 M0 MODE 0 0 0 0 0 0 1 1 x 1 0 2 x 1 1 3 1 0 0 4 1 0 1 5 BCD Select Binary BCD Counting Bit 0 0 16 BITS BINARY COUNTER 1 BINARY CODED DECIMAL BCD COUNTER 4 DIGITAL Note The count of the binary counter is from 0 up to 65 535 and the count of the BCD counter is from 0 up to 9 999 Mode Definitions In 8254 six operating modes can be selected they are Mode 0 Inter...

Page 55: ...Operation Theorem 47 Mode 5 Hardware Triggered Strobe All detailed description of these six modes are written in Intel Microsystems Components Handbook Volume II Peripherals ...

Page 56: ... Ø Calibration program Once the program is executed it will guide you to do the calibration This program is included in the delivered package Ø A 5 1 2 digit multimeter 6 1 2 is recommended Ø A voltage calibrator or a very stable and noise free DC voltage generator 6 2 VR Assignment There are 6 variable resistors VR on the ACL 8112DG HG board to allow you making accurate adjustment on A D and D A ...

Page 57: ...as 5V i e the gain 1 and input mode Bipolar 2 Short the A D channel 0 pin 1 of CN3 to ground GND and connect the TP1 and TP2 with your DVM Trim the variable resister VR5 to obtain a value as close as possible to 0V For ACL 8112DG users can skip this step 3 Applied a 5V input signal to A D channel 0 and trim the VR2 to obtain reading between 4094 4095 4 Applied a 0V input signal to A D channel 0 an...

Page 58: ...and BASE 5 3 Trim the variable resister VR3 to obtain 5V reading in the DVM D A CH2 calibration 1 Connect VDM to CN3 pin 32 AO2 and VDM to A GND 2 Write the digital value 0x0FFF into registers Base 6 and 7 3 Trim the variable resister VR4 to obtain 5V reading in the DVM A calibration utility is supported in the software diskette which is included in the product package The detailed calibration pro...

Page 59: ...xed A D channel A lot of demonstration programs are included in this disk It will help you understand the library more quickly The detailed description of each function in the library is specified in the following sections Please note that the function name is using the following convensions _8112XX_function For ACL 8112DG and ACL 8112HG the function name is for example _8112_function For ACL 8112...

Page 60: ...12 Low Gain card Ver B A8112C_HG 8112 High Gain card Ver C A8112C_DG 8112 Low Gain card Ver C Note the difference between Ver B and Ver C is Multi Scan Register The control code for different version has a little difference For details please refer hardware manual for each ACL 8112 card base_address the I O port base address of the card the default address on the hardware setting is Hex 220 Return...

Page 61: ...C Language Library 53 ErrCode _8112_Initial CARD_2 A8112B_DG 0x220 if ErrCode ERR_NoError exit 0 ...

Page 62: ...ch_Card_No int card_number int _8112pg_Switch_Card_No int card_number Argument card_number The card number to be initialized only two cards can be initialized the card number must be CARD_1 or CARD_2 Return Code ERR_NoError ERR_InvalidBoardNumber Example include 8112 h main _8112_Initial CARD_1 A8112B_HG 0x210 _8112_Initial CARD_2 A8112B_DG 0x220 Assume NoError when Initialize ACL 8112 _8112_Switc...

Page 63: ...TE or DI_HI_BYTE DI_LO_BYTE bit 0 bit 7 DI_HI_BYTE bit8 bit15 data return value from digital port Return Code ERR_NoError ERR_BoardNoInit ERR_PortError Example See Demo program Demo Program DI_DEMO C 7 4 _8112_DI _Channel Description This function is used to read data from digital input channels bit There are 16 digital input channels on the ACL 8112 When performs this function the digital input p...

Page 64: ...ARD_1 A8112B_HG 0x220 Assume NoError when Initialize ACL 8112 for ch 0 ch 16 ch _8112_DI_Channel ch data printf The value of DI channel d is d n ch data 7 5 _8112_DO Description This function is used to write data to digital output port There are 16 digital outputs on the ACL 8112 they are divided by two ports DO_LO_BYTE and DO_HI_BYTE The channel 0 to channel 7 are defined in DO_LO_BYTE port and ...

Page 65: ...ERR_PortError Example include 8112 h main _8112_Initial CARD_1 A8112B_DG 0x220 Assume NoError when Initialize ACL 8112 DG ver B card _8112_DO DO_LO_BYTE 0x55 printf The low byte is now 0x55 n _8112_DO DO_HI_BYTE 0xAA printf The high byte is now 0xAA n A more detailed program is provided in this software DO_DEMO C 7 6 _8112_DA Description This function is used to write data to D A converter There a...

Page 66: ...58 C Language Library resolution of each channel is 12 bit i e the digital data range is from 0 to 4095 Syntax int _8112_DA int da_ch_no unsigned int data int _8112pg_DA int da_ch_no unsigned int data ...

Page 67: ...e hardware setting for DA output range is 0 5V _8112_DA DA_CH_1 0x800 printf The output voltage of CH1 is 2 5V n _8112_DA DA_CH_2 0xFFF printf The output voltage of CH2 is 5V n A more complete program is provided in this software DA_DEMO C 7 7 _8112_AD_Input_Mode Description This function is only useful for ACL 8112 ver B series The ACL 8112 can offer either 16 single ended analog input channels o...

Page 68: ...in int j _8112_Initial CARD_1 A8112B_DG 0x210 Assume ERR_NoError when Initialize ACL 8112 _8112_Initial CARD_2 A8112B_HG 0x220 Assume ERR_NoError when Initialize ACL 8112 _8112_AD_Input_Mode DIFFERENTIAL set analog input mode as differential mode if this function is not called the default input mode is single ended mode for j 0 j 7 j _8112_AD_Set_Channel j printf AD channel d is now selected n j _...

Page 69: ...C Language Library 61 _8112_AD_Set_Channel j printf AD channel d is now selected n j the following A D s operation is based on channel 3 ...

Page 70: ...nt _8112_AD_Set_Channel int ad_ch_no int _8112pg_AD_Set_Channel int ad_ch_no Argument ad_ch_no channel number to perform AD onversion for single ended mode channel no is from 0 15 for differential mode channel no is from 0 7 Return Code ERR_NoError ERR_BoardNoInit ERR_InvalidADChannel Example include 8112 h main _8112_Initial CARD_1 A8112B_DG 0x220 Assume NoError when Initialize ACL 8112 _8112_AD_...

Page 71: ...C Language Library 63 ...

Page 72: ... type is bipolar which are pre set by the ACL 8112 hardware The relationship between analog input voltage range gain and input mode are specified by following tables this table is suitable for ACL 8112HG high gain card AD_INPUT GAIN Input type Bipolar or Unipolar Input Range AD_B_5_V 1 Bipolar 5V AD_B_0_5_V 10 Bipolar 0 5V AD_B_0_05_V 100 Bipolar 0 05V AD_B_0_005_V 1 000 Bipolar 0 005V AD_U_10_V 1...

Page 73: ...AD_U_2_5_V 4 Unipolar 0V 2 5V AD_U_1_25_V 8 Unipolar 0V 1 25V For ACL 8112DG card the gain values suppst 1 2 4 8 and 16 The initial value of gain is 1 The relationship between gain and input voltage ranges is specified by following tables when input voltage range is set to 5 V JP9 Gain Code Gain Input Range V AD_GAIN_1 X 1 5 V AD_GAIN_2 X 2 2 5 V AD_GAIN_4 X 4 1 25 V AD_GAIN_8 X 8 0 625 V AD_GAIN_...

Page 74: ...lude 8112 h main _8112_Initial CARD_1 A8112B_HG 0x220 Assume NoError when Initialize ACL 8112 _8112_AD_Input_Mode DIFFERENTIAL set analog input mode as differential mode _8112_AD_Set_Range AD_B_5_V printf The A D analog input range is 5V n for j 0 j 7 j _8112_AD_Set_Channel j printf AD channel j is now selected n all analog input operations are based on analog differential mode input range is from...

Page 75: ...imer Trigger DMA Transfer AD_MODE_3 External Trigger DMA Transfer AD_MODE_4 External Trigger Interrupt Transfer AD_MODE_5 Software Trigger Interrupt Transfer AD_MODE_6 Timer Trigger Interrupt Transfer AD_MODE_7 Not Used Note All analog input modes selection should be go with hardware settings which is described in the hardware users manual Syntax int _8112_AD_Set_Mode int ad_mode int _8112pg_AD_Se...

Page 76: ...d the converted data should be transfered in the interrupt service routine ISR 7 11 _8112_AD_Soft_Trig Description This function is used to trigger the A D conversion by software When the function is called a trigger pulse will be generated and the converted data will be stored in the base address Base 4 and Base 5 and can be retrieved by function _8112_AD_Acquire Please refer to section 7 12 Synt...

Page 77: ...n is used to poll the AD conversion data It will trigger the AD conversion and read the 12 bit A D data when the data is ready data ready bit becomes low Syntax int _8112_AD_Aquire int ad_data int _8112pg_AD_Aquire int ad_data Argument ad_data 12 bit A D converted value the value should within 0 to 4095 Return Code ERR_NoError ERR_BoardNoInit ERR_AD_AquireTimeOut Example include 8112 h main int ad...

Page 78: ...is d n ad_data else printf AD conversion error happen n Also see deme program AD_DEMO C 7 13 _8112_CLR_IRQ Description This function is used to clear interrupt request which requested by the ACL 8112 If you use interrupt to transfer A D converted data you should use this function to clear interrupt request status otherwise no new coming interrupt will be generated Syntax int _8112_CLR_IRQ void int...

Page 79: ... in the background which will not be stop until the Nth conversion has been completed or your program execute _8112_AD_DMA_Stop function to stop the process After executing this function it is necessary to check the status of the operation by using the function _8112_AD_DMA_Status The function is performed on single A D channel with fixed analog input range ...

Page 80: ...r DMA_CH_1 or DMA_CH_3 Note Make sure your hardware configuration is set to right DMA channel irq_ch_no IRQ channel number used to stop DMA Note Make sure your hardware configuration is set to right IRQ interrupt level count the number of A D conversion ad_buffer the start address of the memory buffer to store the AD data the buffer size must large than the numbers of AD conversion c1 the 16 bit t...

Page 81: ...C Language Library 73 Example See Demo Program AD_Demo4 C ...

Page 82: ...count the number of A D data which has been transferred Return Code ERR_NoError ERR_BoardNoInit ERR_AD_DMANotSet Example See demo program AD_Demo4 C 7 16 _8112_AD_DMA_Stop Description This function is used to stop the DMA data transfer After executing this function the internal A D trigger is disable and the A D timer timer 1 and 2 is stopped The function returns the number of the data which has b...

Page 83: ... After executing this function it is necessary to check the status of the operation by using the function 8112_AD_INT_Status The function is performed on single A D channel with fixed analog input range Syntax int _8112_INT_Start int ad_ch_no int ad_range int irq_ch_no int count int ad_buffer unsigned int c1 unsigned int c2 int _8112pg_INT_Start int ad_ch_no int ad_gain int irq_ch_no int count int...

Page 84: ...nge ERR_InvalidIRQChannel ERR_InvalidTimerValue Example See demo Program AD_Demo2 C 7 18 _8112_AD_INT_Status Description Since the _8112_AD_INT_Start function is executed in background you can issue the function _8112_AD_INT_Status to check the status of interrupt operation Syntax int _8112_AD_INT_Status int status int count int _8112pg_AD_INT_Status int status int count Argument status status of ...

Page 85: ...C Language Library 77 ERR_AD_INTNotSet Example See demo program AD_Demo2 C ...

Page 86: ... count the number of A D data which has been transferred Return Code ERR_NoError ERR_BoardNoInit ERR_AD_INTNotSet Example See Demo Program AD_Demo2 C 7 20 _8112_AD_Timer Description This function is used to setup the Timer 1 and Timer 2 Timer 1 2 are used as frequency divider for generating constant A D sampling rate dedicatedly It is possible to stop the pacer trigger by setting any one of the di...

Page 87: ...l be stopped Return Code ERR_NoError ERR_BoardNoInit ERR_InvalidTimerValue Example main int ErrCode _8112_Initial CARD_1 A8112B_HG 0x220 Assume ERR_NoError when Initialize ACL 8112 _8112_AD_Timer 10 10 set AD sampling rate to 2MHz 10 10 _8112_AD_Timer 0 0 stop the pacer trigger 7 21 _8112_TIMER_Start Description The Timer 0 on the ACL 8112 can be freely programmed by the users This function is use...

Page 88: ...80 C Language Library be used as frequency generator if internal clock is used It also can be used as event counter if external clock is used All the 8253 mode is available ...

Page 89: ...he counter value of timer Return Code ERR_NoError ERR_BoardNoInit ERR_InvalidTimerMode ERR_InvalidTimerValue Example See demo program TMR_DEMO C 7 22 _8112_TIMER_Read Description This function is used to read the counter value of the Timer 0 Syntax int _8112_TIMER_Read unsigned int counter_value int _8112pg_TIMER_Read unsigned int counter_value Argument counter_value the counter value of the Timer...

Page 90: ...ith counter value 0 That is the clock output signal will be set to high after executing this function Syntax int _8112_TIMER_Stop unsigned int counter_value int _8112pg_TIMER_Stop unsigned int counter_value Argument counter_value the current counter value of the Timer 0 Return Code ERR_NoError ERR_BoardNoInit Example See demo program TMR_DEMO C ...

Page 91: ... D conversion uses software trigger and program data transfer AD_DEMO2 C A D conversion uses interrupt and program data transfer AD_DEMO3 C A D conversion uses DMA data transfer AD_DEMO4 C A D conversion uses multiple channels and input range programmable triggers by PC timer and saves all data to a file ad_demo4 data DA_DEMO C D A conversion DI_DEMO C Read data from digital input channels DO_DEMO...

Page 92: ...g its specifications or if the serial number has been removed Seller does not assume any liability for consequential damages as a result from our products uses and in any event our liability shall not exceed the original selling price of the equipment The equipment warranty shall constitute the sole and exclusive remedy of any Buyer of Seller equipment and the sole and exclusive liability of the S...

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