Novatek NT6862-5 Series, Manual, Page: 5 / 57

NT6862-5xxxx
5
Pin Description (continued)
Pin No. Designation Reset Init. I/O Description
40 Pin 42 Pin
36 38 DAC5/SDA1
[ MODE2 ]
O
[ I ]
Open drain 5V, D/A converter output 5, shared with open
drain SDA1 line of I
2 C bus, Schmitt Trigger buffer
[ OTP ROM mode select ]
37 39 DAC4/SCL1
[ MODE1 ]
O
[ I ]
Open drain 5V, D/A converter output 4, shared with open
drain SCL1 line of I
2 C bus, Schmitt Trigger buffer
[ OTP ROM mode select ]
38 40 DAC3
[ MODE0 ]
O
[ I ]
Open drain 5V, D/A converter output 3
[ OTP ROM mode select ]
39 41 HSYNCI I Debouncing & Schmitt Trigger input pin for video
horizontal sync signal internally pulled high, shared with
composite sync input. A jitter filter is added at the front
end, it could effectually reduce the jitter interference of
external noisy Hsync input.
40 42 VSYNCI/INTV
[ A14 ]
VSYNCI I
[ I ]
Debouncing & Schmitt Trigger input pin for video vertical
sync signal, internal pull high, shared with input pin of
external interrupt source intv with Schmitt Trigger,
selectable triggered, and internal pulled up 22K
Ω
register
[ OTP ROM program address buffer ]
- 6 P40 I/O
Bi-directional I/O pin with internal pulled up 22K
Ω
register, only 42 pin S-DIP available
- 37 P41 I/O
Bi-directional I/O pin with internal pulled up 22K
Ω
register, only 42 pin S-DIP available
* This RESET pin must be pulled high by an external pulled-up register (5K
Ω
suggestion), or it will remain in low voltage
and continually keep the system in a rest state..