NT6862-5xxxx
3
Pin Description
Pin No.
40 Pin
42 Pin
Designation
Reset Init.
I/O
Description
1
1
DAC2
[ PGM ]
O
[ I ]
Open drain 5V, D/A converter output 2
[OTP ROM program control]
2
2
DAC1/ADC3
DAC1
O
Open drain 5V, D/A converter output 1, shared with A/D
converter channel 3 input
3
3
DAC0/ADC2
[ OE ]
DAC0
O
Open drain 5V, D/A converter output 0, shared with A/D
converter channel 2 input
[OTP ROM program output enable]
4
4
RESET
[ VPP ]
I
[ P ]
Schmitt Trigger input pin, low active reset with internal
pulled down 50K
Ω
register *
[OTP ROM program supply voltage]
5
5
V
DD
P
Power
6
7
GND
P
Ground
7
8
OSCO
O
Crystal OSC output
8
9
OSCI
I
Crystal OSC input
9
10
P15/INTE0
I/O
Bi-directional I/O pin with internally pulled up 22K
Ω
register, shared with input pin of external interrupt source0
(NMI), with Schmitt Trigger, selectable triggered, and
internally pulled up 22K
Ω
register
10
11
P14/PATTERN
[ A15/CE ]
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
Ω
register, shared with the output of self test pattern
[ OTP ROM program address buffer & chip enable ]
11
12
P13/HALFI
[ A11 ]
P13
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
Ω
register, shared with half Hsync input.
[ OTP ROM program address buffer ]
12
13
P12/HALFO
[ A10 ]
P12
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
Ω
register, shared with half Hsync output
[ OTP ROM program address buffer ]
13
14
P11/ADC1
[ A9 ]
P11
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
Ω
register,
shared with A/D converter channel 1 input
[ OTP ROM program address buffer ]
14
15
P10/ADC0
[ A8 ]
P10
I/O
[ I ]
Bi-directional I/O pin with internally pulled up 22K
Ω
register,
shared with A/D converter channel 0 input
[ OTP ROM program address buffer ]
15
16
P16/INTE1
P16
I/O
Bi-directional I/O pin with internally pulled up 22K
Ω
register,
shared with input pin of external interrupt source1, with
Schmitt Trigger, selectable triggered, and an internal pulled
up 22K
Ω
register