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NT6862-5xxxx

2

Pin Configurations

40-Pin P-DIP

[PGM] DAC2

DAC1/ADC3

[OE] DAC0/ADC2

[DB7] P27

[VPP] RESET

V

DD

GND

OSCO

OSCI

[CE] P14/PATTERN

[A10] P12/HALFO

[A9] P11/ADC1

[A8] P10/ADC0

P20 [DB0]

P07/HSYNCO [A7]

P31/SCL0 [A13]

DAC4/SCL1 [MODE1]

DAC3 [MODE0]

HSYNCI

VSYNCI/INTV [A14]

NT6862

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

P15/INTE0

[A11] P13/HALFI

P16/INTE1

17

18

19

20

24

23

22

21

DAC5/SDA1 [MODE2]

DAC6 [RESET]
CREG

P21 [DB1]

P22 [DB2]

P06/VSYNCO [A6]
P05/DAC12 [A5]

P04/DAC11 [A4]

P03/DAC10 [A3]
P02/DAC9 [A2]

P01/DAC8 [A1]

P00/DAC7 [A0]

P30/SDA0 [A12]

[DB6] P26

[DB5] P25

[DB4] P24

[DB3] P23

* [    ]: OTP Mode

42-Pin S-DIP

[PGM] DAC2

DAC1/ADC3

[OE] DAC0/ADC2

[VPP] RESET

V

DD

P40

GND

OSCO

OSCI

P15/INTE0

[A11] P13/HALFI

[A9] P11/ADC1

[A8] P10/ADC0

P00/DAC7 [A0]

P16/INTE1

P01/DAC8 [A1]

P02/DAC9 [A2]

P03/DAC10 [A3]

P04/DAC11 [A4]

P06/VSYNCO [A6]

P07/HSYNCO [A7]

DAC6 [RESET]

P41

DAC5/SDA1 [MODE2]

DAC4/SCL1 [MODE1]

DAC3 [MODE0]

HSYNCI

VSYNCI/INTV [A14]

CREG

NT6862U

1

2

3
4

5

6

7

8

9

10

11

12

13

14

15

16

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

[CE] P14/PATTERN

[A10] P12/HALFO

[DB7] P27

[DB6] P26

[DB5] P25

[DB4] P24

[DB3] P23

17

18

19

20

21

P05/DAC12 [A5]

P31/SCL0 [A13]

P30/SDA0 [A12]

P20 [DB0]

P21 [DB1]

P22 [DB2]

26

25

24

23

22

* [    ]: OTP Mode

Block Diagram

Timing Generator

CPU core

6502

Interrupt
Controller

H/V Sync Signals

Processor

SRAM + STACK

512 Bytes

Watch Dog Timer

PWM DACs

I/O Ports

OSCI

OSCO

V

DD

GND

HSYNCI

INTE0/1

SCL0

SDA0

DAC0 - DAC7

P00 - P07

P10 - P16

P30 - P31

VSYNCO

 A/D Converter

ADC0 - ADC3

8-Bit Base Timer

P40 - P41

IIC BUS

P20 - P27

HSYNCO

HALFI

HALFO

DAC8 - DAC12

VSYNCI/INTV

OTP Program ROM

32K Bytes

PATTERN

SCL1

SDA1

Voltage

Regulator

CREG

Summary of Contents for NT6862-5 Series

Page 1: ...1 Shift Register INT INTRX0 1 Shift Register INT INTNAK0 1 No Acknowledge INTSTOP0 1 Stop Condition Occurred INT INTE1 External INT with Selectable Edge Trigger INTV VSYNC INT INTMR Base Timer INT IN...

Page 2: ...HALFI A9 P11 ADC1 A8 P10 ADC0 P00 DAC7 A0 P16 INTE1 P01 DAC8 A1 P02 DAC9 A2 P03 DAC10 A3 P04 DAC11 A4 P06 VSYNCO A6 P07 HSYNCO A7 DAC6 RESET P41 DAC5 SDA1 MODE2 DAC4 SCL1 MODE1 DAC3 MODE0 HSYNCI VSYN...

Page 3: ...ister 10 11 P14 PATTERN A15 CE I O I Bi directional I O pin with internally pulled up 22K register shared with the output of self test pattern OTP ROM program address buffer chip enable 11 12 P13 HALF...

Page 4: ...I O I Bi directional I O pin with internally pulled up 22K register shared with open drain 5V D A converter output 10 OTP ROM program address buffer 29 30 P03 DAC10 A3 P03 I O I Bi directional I O pi...

Page 5: ...ith composite sync input A jitter filter is added at the front end it could effectually reduce the jitter interference of external noisy Hsync input 40 42 VSYNCI INTV A14 VSYNCI I I Debouncing Schmitt...

Page 6: ...ges and interrupt input options The CPU clock cycle is 4MHz 8MHz system clock divided by 2 Please refer to the 6502 data sheet for more detailed information Accumulator A Index Register Y 0 7 7 Index...

Page 7: ...plus Branch on N 0 BRK Break Forced Interrupt PC 2 PC BVC Branch if overflow clears Branch on V 0 BVS Branch if overflow sets Branch on V 1 CLC Clear carry 0 C CLD Clear decimal mode 0 D CLI Clear in...

Page 8: ...register from stack P ROL Rotate left through carry C M7 M0 C ROR Rotate right through carry C M7 M0 C RTI Return from interrupt P PC RTS Return from subroutine PC PC 1 PC SBC Subtract with borrow A...

Page 9: ...2 default stack pointer is 01FF programmers must set S register to FFH when starting the program as LDX FF TXS RAM Unused ROM 0000 0080 8000 FFFF stack pointer FFFE FFFD FFFC RST L RST H IRQ L IRQ H R...

Page 10: ...OLO VPOLO R 0007 HV CON FFH ENHOUT ENHOUT HPOLO VPOLO W 0008 HCNT L 00H HCL7 HCL6 HCL5 HCL4 HCL3 HCL2 HCL1 HCL0 R HCNTOV HCH3 HCH2 HCH1 HCH0 R 0009 HCNT H 00H CLRHOV W 000A VCNT L 00H VCL7 VCL6 VCL5 V...

Page 11: ...NAK0 CLRSTOP0 W INTS1 INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 R 001D IRQ1 00H CLRS1 CLRA1 CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1 W INTADC INTV INTE1 INTMR R 001E IRQ2 00H CLRADC CLRV CLRE1 CLRMR W Selection of E...

Page 12: ...DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW 0033 DACH3 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW 0034 DACH4 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW 0035 DACH5 80H D...

Page 13: ...er from a POWER DOWN condition During the time that this reset pin is held LOW writing to or from the C is inhibited The reset line must be held LOW for at least two CPU clock cycles When a positive e...

Page 14: ...vailable at the activated A D channel The analog voltage to be measured should be stabled during the conversion operation and the variation will not exceed LSB for the best accuracy in measurement Add...

Page 15: ...respondent I O pin will be switched to PWM output pin The PWM refresh rate is 62 5KHz operating on 8MHz system clock There are 13 readable DACH registers corresponding to 13 PWM channels 0030 003D Eac...

Page 16: ...K9 ENDK8 ENDK7 W 0010 ENADC FFH CSTA ENADC3 ENADC2 ENADC1 ENADC0 W 0030 DACH0 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW 0031 DACH1 80H DKVL7 DKVL6 DKVL5 DKVL4 DKVL3 DKVL2 DKVL1 DKVL0 RW 0...

Page 17: ...ddresses FFFE FFFF then transferring program control to the memory vector located at these addresses For NMI interrupt C will transfer execution sequence to the memory vector located at addresses FFFA...

Page 18: ...y INT It will be activated at DDC2 mode when transmission buffer IIC_TXDAT is empty at TRAMISSION mode INTRX INT Receiving Buffer Overflow INT It will be activated at DDC2 mode when new data have stor...

Page 19: ...system The NMI group is also oprating the same procedure as IRQ groups Polling Interrupts When NMI interrupt occurrs at NMI interrupt service routine users must poll the INTE0 INTMUTE bit in the NMIPO...

Page 20: ...0 INTRX0 INTNAK0 INTSTOP0 RW 001A IEIRQ1 00H INTS1 INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 RW 001B IEIRQ2 00H INTADC INTV INTE1 INTMR RW Control Registers for Polling Read Clearing Write Interrupt Reques...

Page 21: ...AC12 respectively If ENDK7 ENDK12 is set to LOW in ENDAC register P00 P05 will act as DAC7 DAC12 respectively Figure 12 2 After the chip is reset ENDK7 ENDK12 will be in the HIGH state and P00 P05s wi...

Page 22: ...unction in the H V sync processor paragraph After the chip is reset the ENHALF bits will be in HIGH state and P12 P13 will act as I O pins P14 is shared with output pin of self test pattern If users c...

Page 23: ...4 PORT3 P30 P31 PORT3 is an 2 bit bi directional open drain I O port Figure 12 6 Each pin of PORT3 may be bit programmed as an input or output port with open drain structure When PORT3 works as output...

Page 24: ...3 sets of free running signals and special output of test pattern at burn in process when activating the free running output function The NT6862 can properly handle either composite or separate sync...

Page 25: ...H Sync Output Control FREE_RUN Control VSYNC INPUT HSYNC INPUT HSYNCO 0 1 1 0 VSYNCO HCNTL HCNTH Digital Filter VCNTL VCNTH S C V 0 1 V Jitter Filter Schmitt Trigger Digital Filter Schmitt Trigger H s...

Page 26: ...wo other options of interval for user counting the frequency of Hsync pulses If users clear the ENHSEL and set the HSEL bits properly this internal counter counts the Hsync pulses during this system d...

Page 27: ...HSYNCI 2 HSYNCI Composite H sync waveform H OR V 2 s Hsync pulse or no pulse the output signal of Hsync will be inserted HSYNCO Inserted Hsync Pulse VSYNCO Original Hsync Pulse Original Hsync Pulse W...

Page 28: ...q or 12 bits data time interval 16 382 or 32 968 ms 3 Its reciprocal is Hsync time duration 1 Extract VCNTL H 14 bit data 2 14 bits data 8 us Vsync time duration 3 Its reciprocal is Vsync freq Set S C...

Page 29: ...SEN bit in the SYNCON control register to activate this function After reset S C INSEN bits default value is HIGH and clear the VCNT HCNT counter latches to zero Sync output In pin assignment VSYNCO H...

Page 30: ...Hsync counter Users can enable HDIFF comparison by clearing ENHDIFF bit and then preload an difference value to HDIFF0 3 bits in the AUTOMUTE control register 000E The system will latch the new value...

Page 31: ...NT6862 5xxxx 31 1 2 Figure 13 8 Two Types of Testing Pattern Back Porch Back Porch Front Porch Front Porch 64 s VSYNC HSYNC 1 s Video Video Figure 13 9 The Porch of Free Running Self Test Pattern...

Page 32: ...3 Bit2 Bit1 Bit0 R W Control Registers for Synprocessor FFH INSEN HSEL S C R 0006 SYNCON FFH INSEN ENHSEL HSEL S C W FFH HSYNCI VSYNCI HPOLI VPOLI HPOLO VPOLO R 0007 HV CON FFH ENHOUT ENVOUT HPOLO VPO...

Page 33: ...it can be preloaded with a value by writing a value to the BT register write only at any time and then the BT will start to count up from this preloaded value When the BT s value reaches FFH it will...

Page 34: ...ne which users can not access directly These two data buffer cooperate properly For the timing diagram please refer to Figure 15 1 After system resets the I2 C bus interface is in DDC1 mode Data trans...

Page 35: ...RTX1 CLRRX1 CLRNAK1 CLRSTOP1 W Control Register for DDC1 2B of Channel 0 0021 CH0ADDR A0H ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 W 0022 CH0TXDAT 00H TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 W 0023 CH0RXDAT 00H RX7...

Page 36: ...le address Automatic wait state insertion Interrupt generation for status control Detection of START and STOP signals The DDC2B will be activated as SLAVE mode initially Users can switch to MASTER mod...

Page 37: ...37 8 7 6 5 1 8 7 ACK 5 4 3 1 8 6 2 7 1 7 SCL 8 9 1 7 8 9 1 7 8 9 SDA START CONDITION STOP CONDITION ADDRESS R W ACK DATA ACK DATA ACK 4 IIDAT Reg bit stream MSB MSB MSB LSB LSB ACK Figure 15 2 DDC2B D...

Page 38: ...R W b WRITE Mode Timing Diagram a WRITE Mode Data Format DATA 0 A Data transferred from external device From external device to NT6862 From NT6862 to external device A Acknowledge S START P STOP Addre...

Page 39: ...m a Read Mode Data Format From external device to NT6862 From NT6862 to external device A Acknowledge A No acknowledge S START P STOP A A 1 wait DATA A Data transferred from NT6862 NT68P62 Address S R...

Page 40: ...th bit R W that indicates data transfer direction When the NT6862 system receives an address data from an external device it will store it in the CH0RXDAT register The system supports A0 default addre...

Page 41: ...n of SCL transmission clock External device can continue sending next byte data to NT6862 The timing diagram refers to Figure 15 3 User must responde a NAK signal in advance to stop the transmission T...

Page 42: ...1 Mode MD_CON 1 Other INT Service yes No Need Polling INTV No INTRX yes yes Read One Byte Data From CH0RXDAT Reg No Put FF Into CH0TXDAT Reg release SDA line yes No Need Polling INTRX Open INTTX INTNA...

Page 43: ...is one byte data received and user can read out by accessing CH0RXDAT control register At the same time if the user responded an ACK signal beforehand the shift register will send out an ACK bit low...

Page 44: ...DDC2B MASTER READ Mode Timiing wait DATA 1 2 3 4 5 6 7 8 A If user read out first byte data from RXDAT buffer system will respond ACK NAK or REPeat START Before user reads out this byte data from RXD...

Page 45: ...inate this communication he can set MODE 1 to send out STOP condition or clear RSTART 0 to send out REPEAT START System will wait if user didn t send out the first byte data As user loaded one byte da...

Page 46: ...1 INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1 R 001D IRQ1 00H CLRS1 CLRA1 CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1 W INTADC INTV INTE1 INTMR R 001E IRQ2 00H CLRADC CLRV CLRE1 CLRMR W Control Register for DDC1 2B of Ch...

Page 47: ...Flag No Yes No Yes ENDDC 0 Send NO_ACK Set Last Byte Flag MODE 0 Send Address Open INTTX INTNAK ENDDC 0 Send Address Send Repeat Start Set Last Byte Flag Open INTTX INTNAK ENDDC 0 No Just Recv One By...

Page 48: ...TOP yes No Need Polling INTNAK No INTTX Yes Yes No Yes No Need Polling INTTX Last byte Trans Send repeat start Trans over close INT interrupt send repeat start Yes No Figure 15 11 Master Mode INT Oper...

Page 49: ...2 5 KHz A D Converter Channel 2 channels 4 channels 6 bit resolution V Counter Bit No 12 Bits handle Vsync freq down to 30 5Hz 14 Bits handle Vsync freq down to 7 6Hz H Interval 8 192 ms 16 384 32 768...

Page 50: ...1 P30 P31 pins VjitterH Input Jitter Low Voltage 1 6 2 0 V HSYNCI VjitterL Input Jitter High Voltage 1 0 1 4 V HSYNCI IIH Input High Current 200 350 A P00 P07 P10 P16 P20 P27 P40 P41 VSYNCI HSYNCI HAL...

Page 51: ...NT6862 5xxxx 51 HSYNCI VSYNCI HALFI VjitterH 1 8V VjitterL 1 2V VIL 0 8V VIH 2 2V t V HSI HSO...

Page 52: ...ay Refer Figure 13 5 tRESET Reset Pulse Width Low 2 tCYCLE tCYCLE 2 Fsys Fvsync Vsync Input Frequency 25K Hz tVSYNC 1 Fvsync tVPW Vsync Input Pulse Width 8 2000 s Fhsync Hsync Input Frequency 120 KHz...

Page 53: ...Vsync High Time 0 50 2000 s Fvsync Vsync Input Frequency 32 25K Hz tVSYNC 1 Fvsync tDD Data Valid 200 500 ns tMODE Time for Transition to DDC2B Mode 500 ns Bit 0 Null Bit Bit 7 Bit 6 SCL SDA VSYNC tMO...

Page 54: ...SCL Clock 1 3 s tHIGH HIGH Period of The SCL Clock 0 8 s tSU STA Set up Time for a Repeated START Condition 1 3 s tHD DAT Data Hold Time 200 ns tSU DAT Data Set up Time 300 ns tR Rise Time of Both SD...

Page 55: ...NT6862 5xxxx 55 Ordering Information Part No Packages NT6862 40L P DIP NT6862U 42L S DIP...

Page 56: ...25 B 0 018 0 004 0 46 0 10 0 002 0 05 B1 0 050 0 004 1 27 0 10 0 002 0 05 C 0 010 0 004 0 25 0 10 0 002 0 05 D 2 055 Typ 2 075 Max 52 20 Typ 52 71 Max E 0 600 0 010 15 24 0 25 E1 0 550 Typ 0 562 Max...

Page 57: ...b 0 051 Max 1 3 Max 0 031 Min 0 8 Min b1 0 021 Max 0 53 Max 0 016 Min 0 40 Min c 0 013 Max 0 32 Max 0 010 Min 0 23 Min D 1 1 531 Max 38 9 Max 1 512 Min 38 4 Min E 1 0 551 Max 14 0 Max 0 539 Min 13 7 M...

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