CCS Technical Documentation
Troubleshooting Instructions RF
NPM-10
Issue 1 03/2003
Nokia Corporation Confidential
Page 9
by a ratio based on the selected channel. The divider output is supplied to the phase
detector, which compares the frequency and phase to the 400kHz reference clock. Based
on this comparison, the phase detector controls the charge pump to either charge or dis-
charge the capacitors in the loop filter. By charging/discharging the loop filter, the con-
trol voltage to the VCO changes and the LO frequency will change. Therefore, the PLL will
make the LO frequency stay locked to the 26MHz VCXO frequency.
The loop filter consists of the following components: C639-C641 and R618-R619.
The PLL is operating at twice the channel center frequency when transmitting or receiv-
ing in the PCS band. For the GSM band, the PLL is operating at four times the channel
frequency. Therefore, divide-by-2 and divide-by-4 circuits are inserted between the PLL
output and LO inputs to the PCS and GSM mixers.
The frequency plan is shown in the table that follows:
According to the previous table, the PLL must be able to cover the frequency range
3296.8 MHz to 3979.6 MHz.
Table 1: PLL Frequency Plan
Frequency
Band
Channel #
System Frequency Band [MHz]
PLL Frequency Band [MHz]
GSM RX
TX
128 - 251
869.2 - 893.8
824.2 - 848.8
3476.8 - 3575.2
3296.8 - 3395.2
PCS RX
TX
512 - 810
1930.2 - 1989.8
1850.2 - 1909.8
3860.4 - 3979.6
3700.4 - 3819.6