TFE-4/RV-1
Company Confidential
TF4 Technical Information
Nokia Customer Care
Page 8b-24
Copyright
©
2005
Nokia Corporation.
Issue 2.0 Mar/2005
Company Confidential
tures the address/data bus-state at point B
.
The captured data is compared on a bit by bit
base (MSB–MSB, LSB–LSB), with the data inside memory. If the comparison shows more
equal bits than unequal bits, the data is not inverted before it is send out on the address/
data bus as output data. The result of the comparison is indicated, by using the PS signal
before the data is read (at point C) by the Bus Controller. This allows the receiving device
to invert the data before it is read into a register. The valid PS signal needs to be avail-
able in advance before the actual read operation takes place.
Figure 10: Basic reading (Random access)
Write cycle.
The write cycle is initiated by first applying the address to the multiplexed address/data
bus and to the address lines Axx-A16, (Axx is the MSB address for that memory density).
The address latch is transparent from A to B. The address is latched at the rising edge of
the AVD signal. Latching address Axx-A16 is mandatory. The random access time is mea-
sured from a stable address, falling-edge of AVD or falling-edge of CE which ever occurs
last. No clock is provided for a random access. The below figure shows a basic write
waveform.