NF DF 1906, Instruction Manual

Page: 68 / 96

5.5
Status System
DF1906
5-18
5.5.2 Standard Event Status Register
Table 5-4 shows the definition of the standard event status register. When a bit in the standard event
status enable register is set to 1, the corresponding bit in the standard event status register becomes
effective, and when any effective bit in that r egister becomes 1, the ESB bit in the status byte register is
set to 1.
The standard event status register can be read by an *ESR? quer y.
All bits ar e cleared by r eading the register by an *ESR? query, or by us ing a *CLS command, or by
turning the power back on. ( However, the PON bit is set to 1 when the power is turned back on)
Table 5-4 Definition of Standard Event Status Register
Bit Weight Description
PON
(7) 128 Power on bit
This is set to 1 at power on. When this is cleared to 0 by reading
the register, it remains 0 until the power is turned back on.
PON
(6) 64 User request bit
Always 0 (unused)
CME
(5) 32 Command error
When there is a syntax error in the progr am code, this is set to 1.
EXE
(4) 16 Execution error
When the parameter is outs ide the setting range, or when there is
incons istency in the setting, this is set to 1.
DDE
(3) 8 Equipment def inition error
Always 0 (unused)
QYE
(2) 4 Query error
When an attempt is made to read data in an empty buffer for
storing r esponse messages or when data is lost in a buffer for
storing response messages, this is set to 1.
RQC
(1
)
2 Request control
Always 0 (unused)
OPC
(0) 1 Operation complete
When the pr ocessing of the OPC command is all f inished, this is
set to 1.
* This bit is always 0 with this equipment .