PEAK 637 User‘s Guide
BIOS Setup 3-
11
You can select RAS to CAS Delay time in HCLKs of 2/2 or 3/3. The system board designer should set the
values in this field, depending on the DRAM installed. Do not change the values in this fiels unless you change
specifications of the installed DRAM or the installed CPU. The Choice: 2, 3.
SDRAM RAS Precharge Time
Defines the length of time for Row Address Strobe is allowed to precharge. The Choice: 2, 3.
SDRAM CAS latency Time
You can select CAS latency time in HCLKs of 2/2 or 3/3. The system board designer should set the values in
this field, depending on the DRAM installed. Do not change the values in this field unless you change
specifications of the installed DRAM or the installed CPU.
DRAM Data Integrity Mode
Select Parity or ECC (ERROR-CORRECTING CODE), according to the type of installed DRAM.
System Bios Cacheable
Select Enabled allows caching of the system BIOS ROM at F000h-FFFFFh, resulting in better system
performance. However, if any program writes to this memory area, a system error may result
Enabled
BIOS access cached
Disabled
BIOS access not cached
Video BIOS Cacheable
Select Enable allows caching of the video BIOS ROM AT C0000h-F7FFFh, resulting in better video
performance. However, if any program writes to this memory area, a system error may result
Enabled
Video BIOS access cached
Disabled
Video BIOS access not cached
Video RAM Cacheable
Select Enabled allows caching of the video RAM, resulting in better system performance. However, if any
program writes tothis memory area, a system error may result.
8 Bit I/O Recovery Time
The recovery time is the length of time, measured in CPU clocks, which the system will delay after the
completion of an input/output request. This delay takes place because the CPU is operationg so much faster
than the input/output bus that the CPU must be delayed to allow for the completion of the I/O. This itm allows
you to detemine the recovery time allowed for 8 bit I/O. Choices are from NA, 1 to 8 CPU clocks.
16 Bit I/O Recovery Time
This item allows you to determine the recovery time allowed for 16 bit I/O. Choices are from NA, 1 to 4 CPU
clocks
Memory Hole At 15M-16M.
In order to improve performance, certain space in memory can be reserved for ISA cards.. This memory must
be mapped into the memory space below 16 MB.
Enabled
Memory hole supported.
Disabled
Memory hole not supported
Passive Release
When Enabled, CPU to PCI bus accesses are allowed druing passive release. Othersiwe, the arbiter only
accepts another PCI master access to local DRAM. The Choice: Enabled, Disabled.
