3-4 Hardware Functional Overview
MAJOR FUNCTIONAL BLOCKS
The Cyrix M1sc, in a 168-pin PGA packaging, is divided into five major functional blocks:
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Integer Unit
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Floating Point Unit
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Cache Unit
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Memory Management Unit
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Bus Interface Unit
Instructions are executed in the Integer Unit pipeline and in the Floating Point Unit (FPU).
The Cache Unit stores the most recently used data and instructions and provides fast access
to this information for the Integer and Floating Point Units.
When external memory access is required, the physical address is calculated by the Memory
Management Unit and then passed to the Bus Interface Unit (BIU). The BIU provides the
interface between the external system board and the processor’s internal execution and
cache units.
SYSTEM LOGIC CONTROLLER
The System Logic Controller function for the notebook is implemented on the Motherboard
using UMC 8486F notebook Chipset. The UM8486F is an advanced 486 compatible single
chip specially designed for notebook computers and other portable computer. Aside from
supporting almost all 486-based CPUs, the UM8486F also integrates PMU, System Con-
troller, RTC and Peripheral Controller (206) into a single 208 QFP package.
Features Summary:
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System
Fully compatible with IBM PC/AT
Supports AM386/486DXLV, Cyrix 486DLC, M6, M7, TI PotoMAC/D se-
ries, Intel P24C, 24D, S-Series, and IBM Blue Lightning up to 33MHz
Supports Intel, AMD, TI and Cyrix SMI
Supports VESA Local Bus-Master mode
Supports 487SX interface
System Operation Voltage from 3V to 5.5V
Three programmable non cacheable regions
Only 4 TTL required
Summary of Contents for Versa 550 Series
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