NEC V850ES/DJ2 User Manual Download

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User’s Manual U17763EE1V1UD00

Summary of Contents for V850ES/DJ2

Page 1: ...User s Manual V850ES DJ2TM 32 bit System in Package Microcontroller Hardware µPD70F3325 Document No U17763EE1V1UD00 Date Published September 2005 NEC Electronics 2005 Printed in Germany ...

Page 2: ...2 User s Manual U17763EE1V1UD00 ...

Page 3: ...s including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON ...

Page 4: ...hereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Spec...

Page 5: ...de names used in this pamphlet are the trademarks or registered trademarks of their respective owners Product specifications are subject to change without notice To ensure that you have the latest product data please contact your local NEC Electronics sales office ...

Page 6: ...ics America Inc Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 1101 Fax 0211 65 03 1327 Sucursal en España Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Succursale Française Vélizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2...

Page 7: ...ization This system specification describes the following sections Pin function Port function Internal peripheral function Electrical target specification Legend Symbols and notation are used as follows Weight in data notation Left is high order column right is low order column Active low notation xxx pin or signal name is over scored or xxx slash before signal name Memory map address High order a...

Page 8: ...8 User s Manual U17763EE1V1UD00 ...

Page 9: ... of Watchdog Timer 2 48 2 10 A D Converter 49 2 11 Asynchronous Serial Interface A UARTA 50 2 12 3 Wire Serial Interface CSIB 52 2 13 CAN Controller 53 2 14 Interrupt Exception Processing Function 54 2 15 DMA Controller DMAC 55 2 16 Key Interrupt Function 56 2 17 Standby Function 57 2 18 Reset Function 58 2 19 Clock Monitor 59 2 20 Low voltage Detector 60 2 21 Voltage Regulator 61 2 22 Flash Memor...

Page 10: ...102 Chapter 6 Serial Interface 104 6 1 Communication Protocol 104 6 2 Command Table 104 6 2 1 Command Byte 105 6 2 2 Data Bytes 105 6 3 Serial I F Operation 106 6 3 1 Read from MTRC operation 106 6 3 2 Timing of MTRC Read operation 107 6 3 3 MTRC Write operation 108 6 3 4 Timing of MTRC Write operation 109 6 4 External CSIB1 Function EXCSI1 110 6 5 Internal CSIB1 Function 111 6 5 1 Operation of Se...

Page 11: ...ator Oscillation Circuit Characteristics 135 9 4 4 PLL Characteristics 135 9 4 5 Ring OSC Characteristics 135 9 5 Voltage Regulator Characteristics 136 9 6 DC Characteristics 137 9 6 1 Input Output Level 137 9 6 2 Pin Leak Current 138 9 6 3 Specific Power Supply Current 139 9 6 4 Data Retention Characteristics 140 9 7 AC Characteristics 141 9 7 1 EXCLO output timing 142 9 7 2 RESET Interrupt FLMD0...

Page 12: ...12 User s Manual U17763EE1V0UD00 ...

Page 13: ...inout of MTRC 66 Figure 3 2 Type A 1 71 Figure 3 3 Type B 1 71 Figure 3 4 Type B 2 72 Figure 3 5 Type D 1 72 Figure 3 6 Type D 2 73 Figure 3 7 Type D 3 73 Figure 3 8 Type D 4 74 Figure 3 9 Type CLK 74 Figure 3 10 Type MTCS 74 Figure 3 11 Type SCK 75 Figure 3 12 Type SI 75 Figure 3 13 Type SO 75 Figure 4 1 Port Register 0 PMT0 Format 79 Figure 4 2 Port MT0 Mode Register 0 PMMT0 Format 79 Figure 4 3...

Page 14: ... Driver Block Diagram 114 Figure 7 2 Free Running Counter MCNTm Format 115 Figure 7 3 Sin Compare Register MCMPn0 Format 116 Figure 7 4 Cos Compare Register MCMPn1 Format 117 Figure 7 5 Compare Control Register MCMPCn Format 1 2 118 Figure 7 6 Timer Mode Control Register MCNTm Format 1 2 120 Figure 7 7 Restart Timing after Counting Operation Stopped 122 Figure 7 8 Operation of 1 bit Addition 123 F...

Page 15: ... 2 4 Pin I O Circuit Types and Recommended Connection of Unused Pins 33 Table 2 5 Assignment of Key Return Detection Pins 56 Table 2 6 Standby Modes 57 Table 2 7 Mask Options 63 Table 3 1 List of Pin Functions 67 Table 3 2 List of Pin Functions 69 Table 4 1 Alternate Pin Functions 76 Table 4 2 Port MT0 Functions 78 Table 4 3 Port MT1 Functions 80 Table 4 4 Port MT2 Functions 83 Table 4 5 Port MT2 ...

Page 16: ...16 User s Manual U17763EE1V0UD00 ...

Page 17: ...tion instructions bit manipulation instructions etc realised by a hardware multiplier as optimum instructions for digital servo control applications Moreo ver as a real time control system the V850ES FG2 enables extremely high cost performance for appli cations that require a low power consumption such as automotive applications For an overview of the V850ES FG3 refer to V850ES FG2 Introduction on...

Page 18: ...5EJ2V0UD00 2nd edition and further releases MTRC of D_Line In this User s Manual Data Sheet all of the MTRC relevant items and the internal connection or pinout of the D_Line device are regarded 1 4 Internal Connection The following pins of the FG2 device are connected to the MTRC CSI I F SIB1 SOB1 SCKB1 Chip select PCM0 as CS 1 4 1 System in Package SiP Figure 1 1 D_Line SiP CPU CSI CSI RegCTL SM...

Page 19: ... Transfer MSB first Transmission transmission reception mode 1 5 1 Communication The software for the communication between the FG2 device and the MTRC has to manage the I F of the CSIB1 and the PCM0 pin as chip select signal The CSI1B of the FG2 device has been set to master mode because the MTRC CSI is always in slave mode Therefore it is necessary that the CSIB1 sends dummy data if the FG2 devi...

Page 20: ...ternal communication between the FG2 device and the MTRC With special regard to the last byte transfer of the internal communication protocol a switch control will delay the switching until the last byte was transferred between FG2 and the MTRC If PMT4 is in port mode the signal of PMT4 depends only on the settings of the PMT4 SFRs PCM0 CS and MTCS EX_CSIB1 signals 1 EX_CSIB1 signals are in inacti...

Page 21: ...PDL12 PDL11 P74 ANI4 P72 ANI2 P73 ANI3 VDD REGC PDL5 FLMD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 P914 INTP5 P915 INTP6...

Page 22: ...z typ 8 MHz Meter Driver 360 6 channels Ports I O 16 O 16 Connection between FG2 device and MTRC 3 Wire Serial Interface CSI slave mode 8 bit single continuous mode Power Supply voltage range 4 0 V to 5 5 V PMT0 PMT1 PMT2 PMT3 PMT4 MTRC SM11 SM14 SM21 SM24 SM31 SM34 SM41 SM44 SM51 SM54 SM61 SM64 SI SO SCK CS MTRESET MTVDD1 MTVDD2 SMVDD1 SMVDD2 SMVDD3 MTVSS SMVSS1 SMVSS2 SMVSS3 Serial Reg CTL PMT00...

Page 23: ...re Register 51 MCMP51 00H R W 0EH Compare Control Register 5 MCMPC5 00H R W 0FH Compare Register 60 MCMP60 00H R W 10H Compare Register 61 MCMP61 00H R W 11H Compare Control Register 6 MCMPC6 00H R W 12H Timer Mode Control Register 0 MCNTC0 00H R W 13H Timer Mode Control Register 1 MCNTC1 00H R W 20H Port MT0 PMT0 Undefined R W 21H Port MT1 PMT1 Undefined R W 22H Port MT2 PMT2 Undefined R W 23H Po...

Page 24: ...24 User s Manual U17763EE1V1UD00 MEMO ...

Page 25: ...on instructions This microcontroller can also realize a real time control system that is highly cost effective and can be used in automotive instrumentation fields Number of instructions 83 Minimum instruction execution time 50 ns main clock fXX 20 MHz General purpose registers 32 bits 32 Instruction set Power on clear function Low voltage detection function Ring OSC 200 kHz TYP Interrupts excepti...

Page 26: ...ntroller area network Debug clock Debug data input Debug data output Debug mode select Debug reset Power supply for port Ground for port Flash programming mode Interrupt request from peripherals Key return Non maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 7 Port 9 Programmable clock output PCM0 to PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDL0 to PDL13 REGC RESET RXDA0 to RXDA2 SCKB0...

Page 27: ... PCT0 PCT1 PCT4 PCT6 PDL0 to PDL13 P90 to P915 P70 to P715 P50 to P55 P40 to P42 P30 to P39 P10 P11 P00 to P06 16 bit interval timer M 1 ch CSIB 2 ch Watch timer TIQ00 to TIQ10 TIQ01 to TIQ11 TIQ02 to TIQ12 TIQ03 to TIQ13 TOQ00 to TOQ10 TOQ01 to TOQ11 TOQ02 to TOQ12 TOQ03 to TOQ13 TXDA0 to TXDA2 RXDA0 to RXDA2 ASCKA0 UARTA 3 ch CTXD0 CTXD1 CRXD0 CRXD1 CAN 2 ch Instruction queue BCU Watchdog timer ...

Page 28: ...rt CS Port CT Port DL Table 2 2 Pin List Port Pins Pin Name I O Function Alternate Function P00 I O Port 0 7 bit I O port Input output can be specified in 1 bit units TIP31 TOP31 P01 TIP30 TOP30 P02 NMI P03 INTP0 ADTRG P04 INTP1 P05 INTP2 DRST P06 INTP3 P10 I O Port 1 2 bit I O port Input output can be specified in 1 bit units INTP9 P11 INTP10 P30 I O Port 3 10 bit I O port Input output can be spe...

Page 29: ...91 KR7 RXDA1 P92 TIQ11 TOQ11 P93 TIQ12 TOQ12 P94 TIQ13 TOQ13 P95 TIQ10 TOQ10 P96 TIP21 TOP21 P97 SIB1 TIP20 TOP20 P98 SOB1 P99 SCKB1 P910 P911 P912 P913 INTP4 PCL P914 INTP5 P915 INTP6 PCM0 I O Port CM 4 bit I O port Input output can be specified in 1 bit units PCM1 CLKOUT PCM2 PCM3 PCS0 PCS1 I O Port CS 2 bit I O port Input output can be specified in 1 bit units PCT0 PCT1 PCT4 PCT6 I O Port CT 4 ...

Page 30: ... clock input TMP20 P97 SIB1 TOP20 TIP21 External event clock input TMP21 P96 TOP21 TIP30 External event clock input TMP30 P01 TOP30 TIP31 External event clock input TMP31 P00 TOP31 TOP00 Output Timer output TMP00 P32 ASCKA0 TIP00 TOP01 TOP01 Timer output TMP01 P32 ASCKA0 TIP00 TOP00 P33 TIP01 CTXD0 TOP10 Timer output TMP10 P34 TIP10 CRXD0 TOP11 Timer output TMP11 P35 TIP11 TOP20 Timer output TMP20...

Page 31: ...data output UARTA0 P30 TXDA1 Serial transmit data output UARTA1 P90 KR6 TXDA2 Serial transmit data output UARTA2 P38 ASCKA0 Input Baud rate clock input to UARTA0 P32 TIP00 TOP00 TOP01 CRXD0 Input CAN receive data input CAN0 P34 TIP10 TOP10 CRXD1 CAN receive data input CAN1 P37 CTXD0 Output CAN transmit data output CAN0 P33 TIP01 TOP01 CTXD1 CAN transmit data output CAN1 P36 ANI0 to ANI15 Input Ana...

Page 32: ...ection RESET Input System reset input X1 Input Main clock resonator connection X2 XT1 Input Subclock resonator connection XT2 VDD Positive power supply pin for internal circuitry VSS Ground potential for internal circuitry EVDD Positive power supply pin for external circuitry same potential as VDD EVSS Ground potential for external circuitry same potential as VSS BVDD Positive power supply pin for...

Page 33: ...dependently connect to EVDD or EVSS via a resistor Output Leave open P31 RXDA0 INTP7 5 W P32 ASCKA0 TIP00 TOP00 TOP01 P33 TIP01 TOP01 CTXD0 P34 TIP10 TOP10 CRXD0 P35 TIP11 TOP11 P36 CTXD1 5 A P37 CRXD1 5 W P38 TXDA2 5 A P39 RXDA2 INTP8 5 W P40 SIB0 5 W Input Independently connect to EVDD or EVSS via a resistor Output Leave open P41 SOB0 5 A P42 SCKB0 5 W P50 KR0 TIQ01 TOQ01 Input Independently con...

Page 34: ...tly connect to BVDD or BVSS via a resistor Output Leave open PDL0 to PDL4 5 Input Independently connect to BVDD or BVSS via a resistor Output Leave open PDL5 FLMD1 PDL6 to AD13 AVREF0 Directly connect to VDD AVSS FLMD0a Directly connect to VSS REGC RESET 2 X1 X2 XT1 16 Connect to VSS via a resistor XT2 16 Leave open VDD VSS BVDD BVSS EVDD EVSS a If noise that exceeds the noise elimination width is...

Page 35: ...le P ch IN OUT VDD N ch Input enable Data Output disable AVREF0 P ch IN OUT N ch P ch N ch VREF Threshold voltage Comparator Schmitt triggered input with hysteresis characteristics Input enable _ AVSS AVSS Pullup enable Pulldown enable Data Output disable Input enable VDD P ch VDD P ch IN OUT N ch N ch Type 2 Type 5 AF Type 5 Type 11 G ...

Page 36: ...63EE1V1UD00 Figure 2 3 Figure 2 1 Pin I O Circuit Types 2 2 Data Output disable P ch IN OUT VDD N ch Input enable P ch VDD Pullup enable Pullup enable Data Output disable Input enable VDD P ch VDD P ch IN OUT N ch P ch Feedback cut off XT1 XT2 Type 5 A Type 5 W Type 16 ...

Page 37: ... Can be set in input or output mode in 1 bit units The V850ES FG2 has a total of 84 I O ports ports 0 1 3 to 5 7 9 CM CS CT and DL The port con figuration is shown below Figure 2 4 Port Configuration P00 P06 Port 0 P90 P915 Port 9 PCM0 PCM3 Port CM PCS0 PCS1 Port CS PCT0 PCT1 Port CT PCT4 PCT6 PDL0 PDL13 Port DL P30 P39 Port 3 P40 P42 Port 4 P50 P55 Port 5 P70 P715 Port 7 P10 P11 Port 1 ...

Page 38: ...Features Minimum instruction execution time 50 ns at 20 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear General purpose registers 32 bits 32 Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturation operation instructions 32 bit shift instructions 1 clock Load store instructions with long short format Four types of bit man...

Page 39: ...X 4 to 5 MHz In PLL Phase Locked Loop mode fX 4 to 5 MHz fXX 16 to 20 MHz Subclock oscillator sub resonator 32 768 kHz 20 kHz RCR 390 kΩ C 47 pF Multiply 4 function via PLL Phase Locked Loop Clock trough mode PLL mode selectable Ring OSC fR 100 to 400 kHz Internal system clock generation 7 steps fXX fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXT Peripheral clock generation Clock output function Programmable ...

Page 40: ...cillator Port CM Prescaler 1 Prescaler 2 IDLE control HALT control HALT mode CPU clock Peripheral clock Internal system clock Main clock oscillator Main clock oscillator stop control IDLE mode0 1 Selector Selector Selector 1 8 divider Watch timer WT clock CSIB0 clock RSTOP bit Watchdog timer 2 WDT2 clock 1 2 divider Selector IDLE control IDLE mode 0 1 Watch timer clock Prescaler 3 Select oscillato...

Page 41: ...s PWM output Interval timer External event counter operation disabled when clock is stopped One shot pulse output Pulse width measurement function Timer synchronized operation function Free running function External trigger pulse output function Functional Outline Capture trigger input signal 2 External trigger input signal 1 Clock selection 8 External event count input 1 Readable counter 1 Captur...

Page 42: ...PnCNT0 Clear 16 bit counter CCR0 buffer register CCR1 buffer register TPnCTL1 TPnSYE TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0 TPnOPT0 TPnCCS1 TPnCCS0 TPnOVF TPnIOC1 TPnIS3 to TPnIS0 SELCNT0 ISEL04 to ISEL02 ISEL00 TPnIOC0 TPnCE TPnCE INTTPnCC0 TPnCTL0 TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC2 TPnEES1 TPnEES0 TPnETS1 TPnETS0 Selector Selector Selector Selector fXX fXX 2 fXX 4 fXX ...

Page 43: ...lowing operations PWM output Interval timer External event counter operation disabled when clock is stopped One shot pulse output Pulse width measurement function Triangular wave PWM output Timer synchronized operation function Functional Outline Capture trigger input signal 4 External trigger input signal 1 Clock selection 8 External event count input 1 Readable counter 1 Capture compare reload r...

Page 44: ...nEST TQnEEE TQnMD2 TQnMD1 TQnMD0 TQnOPT0 TQnCCS3toTQnCCS0 TQnOVF TQnIOC1 TQnIS7 to TQnIS0 TQnIOC0 TQnOL3 to TQnOL0 TQnOE3 to TQnOE0 TQnCE TQnCE INTTQnCC0 TQnCTL0 TQnCE TQnCKS2 TQnCKS1 TQnCKS0 TQnIOC2 TQnEES1 TQnEES0 TQnETS1 TQnETS0 Selector Selector fXX fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 Selector Internal bus Load Load INTTQnOV INTTQnOV INTTQnCC1 INTTQnCC2 INTTQnCC3 TOQn0 TQnCCR2 CCR2 ...

Page 45: ...occur when the timer overflows Interval function Clock selection 8 Simple counter 1 The simple counter is a counter that does not use a counter read buffer This counter cannot be read during timer count operation Simple compare 1 The simple compare register is a register that does not use a compare write buffer No data can be written to this compare register during timer count operation Compare ma...

Page 46: ...rescaler 3 see Figure 2 10 Block Diagram of Prescaler 3 Remarks 1 fBRG Prescaler 3 output frequency 2 fX Oscillation frequency 3 fXT Subclock frequency 4 fW Watch timer clock frequency 5 INTWT Watch timer interrupt 6 INTWTI Interval timer interrupt Internal bus Watch timer operation mode register WTM fBRG fX fW 24 fW 25 fW 26 fW 27 fW 28 fW 210 fW 211 fW 29 fXT 11 bit prescaler Prescaler 3Note Cle...

Page 47: ... of Prescaler 3 Remark fBGCS Prescaler 3 count clock frequency 1 fBRG Prescaler 3 output frequency 2 fX Oscillation frequency fX fX 8 fX 4 fX 2 fX BGCS00 BGCS01 BGCE0 3 bit prescaler 8 bit counter Output control Match fBGCS fBRG Prescaler mode register 0 PRSM0 Prescaler compare register0 PRSCM0 2 Selector ...

Page 48: ... following non maskable interrupt servicing due to a non maskable interrupt request signal INTWDT2 is not possible Therefore following completion of interrupt servicing perform a system reset Figure 2 11 Block Diagram of Watchdog Timer 2 Remarks 1 fX Oscillation frequency 2 fR Ring OSC clock frequency 3 INTWDT2 Non maskable interrupt request signal from watchdog timer 2 4 WDT2RES Watchdog timer 2 ...

Page 49: ...following functions are provided as operation modes Continuous select mode Continuous scan mode One shot scan mode The following functions are provided as trigger modes Software trigger mode External trigger mode external 1 Timer trigger mode Power fail monitor function conversion result compare function Figure 2 12 Block Diagram of A D Converter ANI0 ANI1 ANI2 ANI13 ANI14 ANI15 ADA0M0 ADA0M1 ADA0...

Page 50: ...nabled status by ORing three types of reception errors It is also generated when receive data is transferred from the shift register to receive buffer register n after completion of serial transfer Transmission enable interrupt INTUAnT Generated when transmit data is transferred from the transmit buffer register to the shift register in the transmission enabled status Character length of transmit ...

Page 51: ...ark n 0 to 2 Internal bus UAnOTP0 UAnCTL0 UAnSTR UAnCTL1 UAnCTL2 Receive shift register UAnRX Filter Selector UAnTX Transmission controller Reception controller Baud rate generator INTUAnR INTUAnT TXDAn RXDAn ASCKA0 fXX to fXX 210 Reception unit Transmission unit Transmit shift register Baud rate generator Selector Internal bus Clock selector ...

Page 52: ...nsfer data length selectable from 8 to 16 bits in 1 bit units Data transfer with MSB or LSB first selectable 3 wireSOBn Serial data output SIBn Serial data input SCKBn Serial clock I O Transmission mode reception mode and transmission reception mode selectable Remark n 0 1 Figure 2 14 Block Diagram of 3 Wire Serial Interface Remark n 0 1 Internal bus CBnCTL2 CBnCTL0 CBnSTR Controller INTCBnR SOBn ...

Page 53: ... reception enabled Transfer rate 1 Mbps max CAN clock input 8 MHz 32 message buffers 2 channels Receive transmit history list function Automatic block transmission function Multi buffer receive block function Mask setting of four patterns is possible for each channel Figure 2 15 Block Diagram of CAN Module Remark n 0 1 CANTXn CANRXn CPU CAN module CAN RAM NPB NEC peripheral I O bus MAC Memory Acce...

Page 54: ...xternal sources Moreover exception processing can be started by the TRAP instruction software exception or by generation of an exception event i e fetching of an illegal opcode exception trap Features Interrupts Non maskable interrupts 2 sources Maskable interrupts External 11 Internal 50 sources 8 levels of programmable priorities maskable interrupts Multiple interrupt control according to priori...

Page 55: ...MA channels Transfer unit 8 16 bits Maximum transfer count 65 536 216 Transfer type Two cycle transfer Transfer mode Single transfer mode Transfer requests Request by interrupts from on chip peripheral I O serial interface timer counter A D converter or interrupts from external input pin Requests by software trigger Transfer targets Peripheral I O Peripheral I O Peripheral I O Internal RAM Figure ...

Page 56: ...ck Diagram Table 2 5 Assignment of Key Return Detection Pins Flag Pin Description KRM0 Controls KR0 signal in 1 bit units KRM1 Controls KR1 signal in 1 bit units KRM2 Controls KR2 signal in 1 bit units KRM3 Controls KR3 signal in 1 bit units KRM4 Controls KR4 signal in 1 bit units KRM5 Controls KR5 signal in 1 bit units KRM6 Controls KR6 signal in 1 bit units KRM7 Controls KR7 signal in 1 bit unit...

Page 57: ...Mode in which all the internal operations of the chip except the oscillator PLLa and flash memory are stopped a The PLL holds the previous operating status in clock through mode or PLL mode IDLE2 mode Mode in which all the internal operations of the chip except the oscillator are stopped Software STOP mode Mode in which all the internal operations of the chip except the subclock oscillator are sto...

Page 58: ...User s Manual U17763EE1V1UD00 2 18 Reset Function The reset function is outlined below Reset function by RESET pin input Reset function by overflow of watchdog timer 2 WDT2RES System reset by low voltage detector LVI System reset by clock monitor CLM ...

Page 59: ...red to 0 by any means other than reset The clock monitor automatically stops under the following conditions While oscillation stabilization time is being counted after software STOP mode is released When the main clock is stopped MCK bit of the PCC register 1 during subclock operation or CLS bit of the PCC register 0 during main clock operation When the sampling clock is stopped Ring OSC When the ...

Page 60: ... in two steps Interrupt or reset signal can be selected by software Can operate in STOP mode too Operation can be stopped by software If the low voltage detector is used to generate a reset signal bit 0 LVIRF of the reset source flag reg ister RESF is set to 1 when the reset signal is generated Figure 2 19 Block Diagram of Low Voltage Detector LVIS0 LVION Detected voltage source VLVI VDD VDD INTLV...

Page 61: ...s product operates in all operation modes normal operation HALT IDLE1 IDLE2 STOP and sub IDLE modes and during reset To stabilize the output voltage of the regulator connect a capacitor 4 7 µFNote to the REGC pin Note Connect the REGC pin as illustrated below Figure 2 21 Connection of REGC Pin REGC Capacitance EVDD I O buffer normal port 3 5 to 5 5 V BVDD I O buffer normal port 3 5 to 5 5 V Regula...

Page 62: ... commonly used in the following development environments and applications For altering software after solder mounting the V850ES FG2 on the target system For differentiating software in small scale production of various models For data adjustment when starting mass production Features 4 byte 1 clock access for instruction fetch access Batch erase or block unit erase Communication with dedicated fl...

Page 63: ... WDT2 Count clock can be selected Overflow signal can be selected from INTWDT2 or WDT2RES Subclock Crystal resonator connection 02H Ring OSC Can be stopped WDT2 Count clock is fixed to Ring OSC Overflow signal is fixed to WDT2RES Subclock Crystal resonator connection 03H Ring OSC Cannot be stopped WDT2 Count clock is fixed to Ring OSC Overflow signal is fixed to WDT2RES Subclock Crystal resonator ...

Page 64: ...0 bit of the OCDM register special register to 0 when you use on chip debug mode Forced reset function The V850ES FG2 can be forcibly reset Break reset function The CPU can be started in the debug mode immediately after reset of the CPU is released Forced break function Execution of the user program can be forcibly aborted however the illegal operation code exception handler first address 00000060...

Page 65: ...er function The execution time of the user program can be measured Peripheral macro operation stop selection function during break Depending on the debugger to be used whether the peripheral macro operates or is stopped during a break can be selected Functions that are always stopped during break Clock monitor Watchdog timer 2 Functions that can operate or be stopped during break however each func...

Page 66: ...MT40 EXSI1 PMT41 EXSO1 PMT42 EXSCK1 IC PMT00 PMT01 PMT02 PMT03 SMVSS2 SMVDD2 PMT17 SM44 PMT16 SM43 PMT15 SM42 PMT14 SM41 PMT13 SM34 PMT12 SM33 PMT11 SM32 PMT10 SM31 SM24 SM23 SM22 SM21 SM14 SM13 SM12 SM11 SMVDD1 SMVSS1 SMVDD3 PMT27 SM64 PMT26 SM63 PMT25 SM62 PMT24 SM61 PMT23 SM54 PMT22 SM53 PMT21 SM52 PMT20 SM51 PMT43 EXCLO CLK MTCS MTRESET IC MTVSS1 SCK SI SO SMVSS3 MTVDD1 MTVDD2 ...

Page 67: ...i Z O Output Port Meter4 PWM Output Signal sin External PMT15 SM42 O Hi Z O Output Port Meter4 PWM Output Signal sin External PMT16 SM43 O Hi Z O Output Port Meter4 PWM Output Signal cos External PMT17 SM44 O Hi Z O Output Port Meter4 PWM Output Signal cos External PMT20 SM51 O Hi Z O Output Port Meter5 PWM Output Signal sin External PMT21 SM52 O Hi Z O Output Port Meter5 PWM Output Signal sin Ext...

Page 68: ...nput Voltage for Meter3 Meter4 External SMVSS2 Ground Potential for Meter3 Meter4 External SMVDD3 Power Supply Input Voltage for Meter5 Meter6 External SMVSS3 Ground Potential for Meter5 Meter6 External CLK I System Clock Input Internal to FG2 CS I Serial Access Enable Internal to FG2 MTCS At DJ2 device shared with PCM0 WAIT pin of FG2 device PCM0 has to be configured to output for internal commun...

Page 69: ...ve open PMT10 SM31 Meter3 PWM Out put Signal sin B 2 Leave open PMT11 SM32 Meter3 PWM Out put Signal sin Leave open PMT12 SM33 Meter3 PWM Out put Signal cos Leave open PMT13 SM34 Meter3 PWM Out put Signal cos Leave open PMT14 SM41 Meter4 PWM Out put Signal sin Leave open PMT15 SM42 Meter4 PWM Out put Signal sin Leave open PMT16 SM43 Meter4 PWM Out put Signal cos Leave open PMT17 SM44 Meter4 PWM Ou...

Page 70: ...y connect to MTVDD or MTVSS via a resistor Output Leave open PMT35Note 1 Input Independently connect to MTVDD or MTVSS via a resistor Output Leave open PMT36Note 1 Input Independently connect to MTVDD or MTVSS via a resistor Output Leave open PMT37Note 1 Input Independently connect to MTVDD or MTVSS via a resistor Output Leave open PMT40 EXSI1 Expand Pin for SI D 2 Input Independently connect to M...

Page 71: ...cuits Each type of port block diagram is as follows Then the type of each port is shown in each chapter 3 3 1 Type A 1 Figure 3 2 Type A 1 3 3 2 Type B 1 Figure 3 3 Type B 1 WR PMMT PMMTmn WRPMT PMTmn RD Address PMTmn Selector Selector WR SM12MC SM12MC SM11 SM14 SM11 SM14 SM21 SM24 SM21 SM24 ...

Page 72: ... 3 Type B 2 Figure 3 4 Type B 2 3 3 4 Type D 1 Figure 3 5 Type D 1 WRPMCMT PMCMTmn WR PMMT PMMTmn WRPMT PMTmn SM31 SM34 SM41 SM44 SM51 SM54 SM61 SM64 Address PMTmn Selector Selector WRPMCMT PMCMT41 WR PMMT PMMT41 WRPMT PMT41 RD Address PMT41 EXSO1 Selector Selector Selector EXSO1 ...

Page 73: ...E1V1UD00 3 3 5 Type D 2 Figure 3 6 Type D 2 3 3 6 Type D 3 Figure 3 7 Type D 3 WRPMCMT PMCMT40 WR PMMT PMMT40 WRPMT PMT40 RD Address PMT40 EXSI Selector Selector EXSI1 WRPMCMT PMCMT42 WR PMMT PMMT42 WRPMT PMT42 RD Address PMT42 EXSCK1 Selector Selector Selector EXSCK1 ...

Page 74: ...UD00 3 3 7 Type D 4 Figure 3 8 Type D 4 3 3 8 Type CLK Figure 3 9 Type CLK 3 3 9 Type MTCS Figure 3 10 Type MTCS WRPMCMT PMCMT43 WR PMMT PMMT43 WRPMT PMT43 RD Address PMT43 EXCLO Selector Selector EXCLO Selector N ch pull down enable CLK CLK N ch pull down enable MTCS MTCS ...

Page 75: ...ion of MTRC Preliminary User s Manual U17763EE1V1UD00 3 3 10 Type SCK Figure 3 11 Type SCK 3 3 11 Type SI Figure 3 12 Type SI 3 3 12 Type SO Figure 3 13 Type SO P ch pull up disable SCK SCK N ch pull down enable SI SI SO SO ...

Page 76: ...ister Please refer to the peripheral function chapter to get more details Remark m 1 2 4 n 0 to 7 Table 4 1 Alternate Pin Functions 1 2 Port name Alternate pin name Setting value when selecting alternate function PMTmn PMMTmn PMCMTmn Remark PMT00 Note 1 0 1 1 PMT01 Note 1 PMT02 Note 1 PMT03 Note 1 PMT10 SM31 0 1 0 1 1 PMT11 SM32 PMT12 SM33 PMT13 SM34 PMT14 SM41 PMT15 SM42 PMT16 SM43 PMT17 SM44 PMT...

Page 77: ...ecause the internally last transferred byte will be finished before the alternate EXCSI1 function will be activated even if the PCM0 MTCS pin signal is 0 Tis has to be regarded if an external component has been connected to the EXCSI1 PMT40 EXSI1 0 1 0 1 1 Connect to SO only if MTCS 0 Note 4 PMT41 EXSO1 Connect to SI only if MTCS 0 Note 4 PMT42 EXSCK1 Connect to _SCK only if MTCS 0 Note 4 PMT43 EX...

Page 78: ... bit I O Port Port I O data specified in 1 bit units Remarks 1 PORT Port PM Port mode register PMC Port mode control register PFC Port function control register 2 available not available Table 4 2 Port MT0 Functions Port Mode Alternate Function TYPE Register PORT PM PMC PMT00 A 1 PMT01 A 1 PMT02 A 1 PMT03 A 1 ...

Page 79: ...PMMT0 This is an 8 bit register used to specify the input mode output mode It can be read and written in 8 bit unit Figure 4 2 Port MT0 Mode Register 0 PMMT0 Format 7 6 5 4 3 2 1 0 Address Initial value PMT0 0 0 0 0 PMT03 PMT02 PMT01 PMT00 0x20 undefined R W R R R R R W R W R W R W PMT0n Output data control n 0 3 0 Output 0 1 Output 1 7 6 5 4 3 2 1 0 Address Initial value PMMT0 1 1 1 1 PMMT03 PMMT...

Page 80: ... alternate function specified in 1 bit units PMCMT1 register Remarks 1 PORT Port PM Port mode register PMC Port mode control register PFC Port function control register 2 available not available Table 4 3 Port MT1 Functions Port Mode Alternate Function TYPE Register PORT PM PMC PMT10 SM31 B 2 PMT11 SM32 B 2 PMT12 SM33 B 2 PMT13 SM34 B 2 PMT14 SM41 B 2 PMT15 SM42 B 2 PMT16 SM43 B 2 PMT17 SM44 B 2 ...

Page 81: ...gister 1 PMMT1 It can be read and written in 8 bit unit Figure 4 4 Port Mode Register 1 PMMT1 Format 7 6 5 4 3 2 1 0 Address Initial value PMT1 PMT17 PMT16 PMT15 PMT14 PMT13 PMT12 PMT11 PMT10 0x21 undefined R W R W R W R W R W R W R W R W R W PMT1n Output data control n 0 7 0 Output 0 1 Output 1 7 6 5 4 3 2 1 0 Address Initial value PMMT1 PMMT17 PMMT16 PMMT15 PMMT14 PMMT13 PMMT12 PMMT11 PMMT10 0x2...

Page 82: ...gister 1 PMCMT1 Format 7 6 5 4 3 2 1 0 Address Initial value PMCMT1 PMCMT17PMCMT16 PMCMT15PMCMT14 PMCMT13PMCMT12 PMCMT11 PMCMT10 0x2A 0x00 R W R W R W R W R W R W R W R W R W PMCMT1n PMMT1n PMCMTn mode control n 0 7 0 0 Output port 0 1 Hi Z output 1 x SM44 output n 7 SM43 output n 6 SM42 output n 5 SM41 output n 4 SM34 output n 3 SM33 output n 2 SM32 output n 1 SM31 output n 0 ...

Page 83: ...vailable 1 SM1SM2 Mode Control Register SM12MC It can be read and written in 8 bit unit Figure 4 6 SM1SM2 Mode Control Register SM12MC Format Table 4 4 Port MT2 Functions Port Mode Alternate Function TYPE Register PORT PM PMC Hi Z SM11 B 1 Hi Z SM12 B 1 Hi Z SM13 B 1 Hi Z SM14 B 1 Hi Z SM21 B 1 Hi Z SM22 B 1 Hi Z SM23 B 1 Hi Z SM24 B 1 7 6 5 4 3 2 1 0 Address Initial value SM12MC SM24HZCSM23HZCSM2...

Page 84: ...ister Hi Z output controllable in 1 bit units PMMT2 PMCMT2 register Remarks 1 PORT Port PM Port mode register PMC Port mode control register PFC Port function control register 2 available not available Table 4 5 Port MT2 Functions Port Mode Alternate Function TYPE Register PORT PM PMC PMT20 SM51 B 2 PMT21 SM52 B 2 PMT22 SM53 B 2 PMT23 SM54 B 2 PMT24 SM61 B 2 PMT25 SM62 B 2 PMT26 SM63 B 2 PMT27 SM6...

Page 85: ...gister 2 PMMT2 It can be read and written in 8 bit unit Figure 4 8 Port Mode Register 2 PMMT2 Format 7 6 5 4 3 2 1 0 Address Initial value PMT2 PMT27 PMT26 PMT25 PMT24 PMT23 PMT22 PMT21 PMT20 0x22 undefined R W R W R W R W R W R W R W R W R W PMT2n Output data control n 0 7 0 Output 0 1 Output 1 7 6 5 4 3 2 1 0 Address Initial value PMMT2 PMMT27 PMMT26 PMMT25 PMMT24 PMMT23 PMMT22 PMMT21 PMMT20 0x2...

Page 86: ...Register 2 PMCMT2 Format 7 6 5 4 3 2 1 0 Address Initial value PMCMT2 PMCMT27PMCMT26 PMCMT25PMCMT24 PMCMT23PMCMT22 PMCMT21PMCMT20 0x2B 0x00 R W R W R W R W R W R W R W R W R W PMCMT2n PMMT2n PMCMTn mode control n 0 7 0 0 Output port 0 1 Hi Z output 1 x SM64 output n 7 SM63 output n 6 SM62 output n 5 SM61 output n 4 SM54 output n 3 SM53 output n 2 SM52 output n 1 SM51 output n 0 ...

Page 87: ...1 Port MT3 functions 8 bit I O port Port I O specified in 1 bit units Note n 0 to 3 Remarks 1 PORT Port PM Port mode register PMC Port mode control register PFC Port function control register 2 available not available Table 4 6 Port MT3 Functions Port Mode Alternate Function TYPE Register PORT PM PMC PMT30 A 1 PMT31 A 1 PMT32 A 1 PMT33 A 1 PMT34Note A 1 PMT35Note A 1 PMT36Note A 1 PMT37Note A 1 ...

Page 88: ...ster 3 PMMT3 It can be read and written in 8 bit unit Figure 4 11 Port Mode Control Register 3 PMMT3 Format Note at DJ2 n 0 to 3 n 4 5 at DJ2 set PMMT3n 1 Input mode n 6 7 set PMMT3n 1 Input mode 7 6 5 4 3 2 1 0 Address Initial value PMT3 PMT37 PMT36 PMT35 PMT34 PMT33 PMT32 PMT31 PMT30 0x23 undefined R W R W R W R W R W R W R W R W R W PMT3nNote Output data control n 0 7 0 Output 0 1 Output 1 7 6 ...

Page 89: ...ter Port mode control mode alternate function specified in 1 bit units PMCMT4 register Remarks 1 PORT Port PM Port mode register PMC Port mode control register PFC Port function control register 2 available not available Table 4 7 Port MT4 Functions Port Mode Alternate Function TYPE Register PORT PM PMC PMT40 EXSI1 D 2 PMT41 EXSO1 D 1 PMT42 EXSCK1 D 3 PMT43 EXCLO D 4 ...

Page 90: ...T4 Format 2 Port Mode Register 4 PMMT4 It can be read and written in 8 bit unit Figure 4 13 Port Mode Register 4 PMMT4 Format 7 6 5 4 3 2 1 0 Address Initial value PMT4 0 0 0 0 PMT43 PMT42 PMT41 PMT40 0x24 undefined R W R R R R R W R W R W R W PMT4n Output data control n 0 3 0 Output 0 1 Output 1 7 6 5 4 3 2 1 0 Address Initial value PMMT4 1 1 1 1 PMMT43 PMMT42 PMMT41 PMMT40 0x29 0xFF R W R R R R ...

Page 91: ...CS 1 each I O status is as follows 7 6 5 4 3 2 1 0 Address Initial value PMCMT4 0 0 0 0 PMCMT43PMCMT42PMCMT41PMCMT40 0x2C 0x00 R W R R R R R W R W R W R W PMCMT43 PMCMT43 mode control 0 I O port 1 EXCLO output PMCMT42 PMCMT42 mode control 0 I O port 1 EXSCK1 output Note PMCMT41 PMCMT41 mode control 0 I O port 1 EXSO1 output Note PMCMT40 PMCMT40 mode control 0 I O port 1 EXSI1 Input Note Pin name S...

Page 92: ...ration function At the first start of the ring oscillator it is uncalibrated and therefore significant deviations from its basic frequency 8 MHz could be possible The Ring Oscillator Unit supplies an autocalibration function With 5 specified calibration pulses at the CS pin of the MTRC therefore PCM0 WAIT pin at the FG2 direct after MTRES release the Ring Oscil lator self calibration unit adjusts ...

Page 93: ...TRESET and MTCS 1 the MRON bit is changed from 0 to 1 by hard ware 2 To save power consumption the Ring Oscillator can be stopped by clearing the MRON bit to 0 After that the MTRC has to be woken up via the PCM0 CS signal The MRCAL register has to be updated too Caution If MRON bit 0 Ring Oscillator stopped for power saving no MTRC register access is possible Therefor the MRON bit can t be set to ...

Page 94: ...MRCAL has to be rewritten manually without auto matic calibration procedure The MRCALERR bit is set to 1 when the ring oscillator calibration is not normally executed This will happen when the pulse width of the calibration pulse at the MTCS pin hasn t got the specified high and low pulse width or the calibration temperature is not in the specified range When the MRON bit is set to 0 ring oscillat...

Page 95: ...rly stored calibration value e g external EEPROM that has followed from the frequency calibration at the specified tempera ture and voltage 5 3 Calibration Procedure To calibrate the Ring Oscillator 5 specified calibration pulses of the same length at the PCM0 pin of the FG2 are necessary To guarantee the maximum deviation of the calibrated Ring Oscillator this calibra tion has to be performed at ...

Page 96: ...etion Set PCM0 pin 1 No calibration error MRCAL register read Store in the EEPROM Yes Yes No MRCALERR bit read No auto control soft control serial communication Set MTCS pin 0 FG2 pin settings SOB1 SCKB1 SIB1 PCM0 Setting to form the specified pulse via PCM0 Timer etc RingOSC oscillation start enable MRINGCTL operation after eliminating noise time of MTCSP pin MTRESET 1 wait for eliminating noise ...

Page 97: ...iagram for Frequency Calibration Ring Oscillator MTRESET pin PCM0 CS pin MRON bit MRCALSF bit MRCALEN bit eliminating noise time Oscillation stabilization time 1st specified pulse 2nd specified pulse H RingOSC oscillation start enable MRINGCTL operation RingOSC count start Calibration start ...

Page 98: ...e 5 5 Flowchart for MTRESET Release Initial Settings Set PCM0 pin 1 Set MRCALEN 0 The value stored in the EEPROM is loaded to the MRCAL register uncalibrated RingOsc is running FG2 pin settings SOB1 SCKB1 SIB1 PCM0 RingOSC oscillation start after eliminating noise time of PCM0 pin MRINGCTL operation is enabled soft control serial communication Ring Oscillator is stopped calibrated RingOsc is runni...

Page 99: ...ES Release Ring Oscillator MTRESET pin PCM0 CS pin MRON bit MRCALSF bit MRCALEN bit eliminating noise time Oscillation stabilization time RingOSC oscillation start enable MRINGCTL operation Calibration start Calibration disable L Autocalibration won t performed even for rising edge at PCM0 CS pin ...

Page 100: ...he FG2 will wake up the Ring Oscillator from its standby mode To switch the Ring Oscillator on again the following procedure has to be fulfilled Figure 5 7 Flowchart for Standby Mode Release Set MRON 0 RingOsc is stopped Set PCM0 CS pin 0 Set PCM0 CS pin 1 The value stored in the EEPROM is loaded to the MRCAL register uncalibrated RingOsc soft control serial communication calibrated RingOsc is run...

Page 101: ... Diagram for Standby Mode Release Ring Oscillator MTRESET pin PCM0 CS pin MRON bit MRCALSF bit MRCALEN bit Eliminating noise time Oscillation stabilization time L L Standby mode MRCALSF bit is 0 autocalibration won t start Autocalibration won t performed even for rising edge at PCM0 CS pin ...

Page 102: ...r consumption can be reduced by stopping the RingOSCs by clearing the MRON bit to 0 Therefore the basic clock supply of the MTRC will be stopped too When after power save mode release the MRON bit is set to 1 again the stored calibration value has to be written to the MRCAL register first If this is not executed the accuracy of the ring oscil lator cannot be guaranteed 7 During power save mode the...

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Page 104: ...bits fixed Transfer direction MSB first Transfer mode Transmit Receive mode Serial clock frequency fSCK fRing Oscillator 4 Remark fSCK Serial Interface clock fRing Oscillator frequency of MTRC Ring Oscillator Communication format 6 2 Command Table 1st byte Command Address 2nd byte to last byte Data Instruction Command Address Data READ I7I6A5A4A3A2A1A0 D7D6D5D4D3D2D1D0 input output WRITE I7I6A5A4A...

Page 105: ...s data which was specified by the address of the Command Byte When the write function is selected the FG2 device outputs data which are written to the MTRC addresses specified by the Command Byte before 7 6 5 4 3 2 1 0 Command RW AUTO A5 A4 A3 A2 A1 A0 RW R W Selection of MTRC 0 Read 1 Write AUTO Operation mode of Communication 0 Disable Continuous transfer 1 Enable Continuous transfer A5 to A0 Ad...

Page 106: ...ia the SI pin If the read command is received the MTRC outputs data via the SO pin which were specified with the address bits A5 to A0 When continuous transfer is selected Auto bit of Command Byte 1 the MTRC outputs next data at the incremented address via the SO pin Figure 6 1 MTRC Operation Flow on Reading END CS 1 No Receive Read Command Address Send Read Data CS 0 Yes Auto 1 No Yes ...

Page 107: ...A2A1A0j I7 I6 A0 After Last data transfer start FG2 can set CS 0 last Data byte will be sent from MTRC READ command READ command READ data READ data INTCSI Dummy Write Dummy Write CS SCK SI SO READ command READ data READ data INTCSI I7 I6 A0 D7 D6 D0 D7 D6 D0 i A5A4A3A2A1A0 1j i A5A4A3A2A1A0 2 j D7 D6 D0 i A5A4A3A2A1A0 j READ data After Last data transfer start FG2 can set CS 0 last Data byte will...

Page 108: ... write next receive data which is specified address When select continuous mode Auto 1 next receive data will be written 1 incremented address When select disable continuous mode Auto 0 After receive 1 byte data MTRC decide that next received data as command address Figure 6 4 Operation Flow on MTRC Writing END CS 1 No Receive Write Command Address Send Write Data CS 0 Yes Auto 1 No Yes ...

Page 109: ...ta I7 I6 A0 D7 D6 D0 I7 I6 A0 i A5A4A3A2A1A0 j D7 D6 D0 i A5A4A3A2A1A0 j WRITE command WRITE command After Last data transfer start FG2 can set CS 0 last Data byte will be received from MTRC I7 I6 A0 D7 D6 D0 D7 D6 D0 i A5A4A3A2A1A0 1j i A5A4A3A2A1A0 2 j D7 D6 D0 i A5A4A3A2A1A0 j WRITE data WRITE data WRITE command WRITE data CS SCK SI SO INTCSI After Last data transfer start FG2 can set CS 0 last...

Page 110: ... refer to Figure 1 2 CS Functionality on page 20 With special regard to the last byte transfer of the internal communication protocol a switch control will delay the switching until the last byte was transferred between FG2 and the MTRC Remarks 1 If the EXCSI1 is used and the CS is set to 0 during the last byte transfer the EXSO1 and EXSI1 signal will be suppressed until the last Byte transfer has...

Page 111: ... first Transmission transmission reception mode Baudrate maximum fRing Oscillator 4 Cautions 1 The internal ring oscillator of the MTRC is not synchronized to the CSIB1 SCKB1 signal Furthermore the MTRC needs time to process the incoming commands and data Therefore the baudrate of the FG2 CSIB1 has to be set to maximum of fRing Oscillator 4 2 After MTRESET release the Ring Oscillator is uncalibrat...

Page 112: ...ion is possible SIO shift operation is synchronised with the falling edge of iSCK The data which is received via SI pin is latched SIO on rising edge of iSCK Figure 6 7 Basic Operation 2 Continuous data transfer In spite of the fix 8 bit mode of the MTRC CSI it supports continuous data transfer mode Therefore the FG2 CSIB1 can set to 16 bit mode and continuous data transfer for the fastest com mun...

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Page 114: ...put 24 Figure 7 1 Meter Controller Driver Block Diagram Selector SM Channel 0 SM Channel 1 SM Channel 2 SM Channel 3 Output Control Circuits 2 fMC0 SM11 SM12 SM13 SM14 SM41 SM42 SM43 SM44 Meter Controller 0 Selector Time Base MCNT1 SM Channel 0 SM Channel 1 Output Control Circuits fMC1 SM51 SM52 SM53 SM54 SM61 SM62 SM63 SM64 Meter Controller 1 Time Base MCNT0 fR fR 16 fR 32 fR 64 fR 128 fR 256 fR ...

Page 115: ...er starts by setting the PCEm bit 1 of MCNTCm register After reaching the value FFH the counter will be overflowed and set itself to 01H MCNTm can t be written or read Figure 7 2 Free Running Counter MCNTm Format The count value is cleared in the following cases RESET 0 PCEm 0 The relation of the duty factor for the PWM output from the SMnm pin is calculated by the following expression PWM duty Se...

Page 116: ...slave register executes at TENn 1 AND when overflow occurs Ensure that the TENn bit 0 i e rewriting time PWM cycle time then set MCMPn0 and the corre sponding TENn bit to 1 The PWM pulse is not output until the first overflow occurs after the counting operation has been started because the compare data is not transferred to the slave beforehand MCMPn0 is set with an 8 bit memory manipulation instr...

Page 117: ...generated MCMP11 to MCMP41 are compared with MCNT0 MCMP51 to MCMP61 are compared with MCNT1 For the handling of the TENn bit please refer to the MCMPn0 register MCMPn1 is set with an 8 bit memory manipulation instruction The value of these register are set to 00H at MTRESET 0 Figure 7 4 Cos Compare Register MCMPn1 Format Note MCNP11 at 0x01 MCNP21 at 0x04 MCNP31 at 0x07 MCNP41 at 0x0A MCNP51 at 0x...

Page 118: ... to 00H Figure 7 5 Compare Control Register MCMPCn Format 1 2 Note MCMPC1 at 0x02 MCMPC2 at 0x05 MCMPC3 at 0x08 MCMPC4 at 0x0B MCMPC5 at 0x0E MCMPC6 at 0x11 Caution Ensure that the time for rewriting the TEN bit is greater then the count period of the MCNTm counter register PWM cycle time Remarks 1 TENn bit is cleared automatically after data transfer from MCMPnm master register to slave register ...

Page 119: ...in the average value will be only 1 2 PWM tick which cor responds with a further bit for the resolution of the PWM value quasi 9 bit resolution ADBn1 Control of 1 bit addition circuit cos side of meter n 0 No 1 bit addition 1 1 bit addition ADBn0 Control of 1 bit addition circuit sin side of meter n 0 No 1 bit addition 1 1 bit addition DIRn1 DIRn0 Control of PWM output pin SMn1 sin SMn2 sin SMn3 c...

Page 120: ...y of register access By setting CAE 0 the count operation is stopped This is used to reduce the power consumption Remark If the CAE bit will be set to 0 the counter MCNTCn register will hold it s value and the PWM output pin will hold its actual Level To clear the counter and set the PWM output pin to inac tive level PCEm 0 has to be set beforehand Remarks 1 the CAE and PCE0 bit can be set simulta...

Page 121: ...liminary User s Manual U17763EE1V1UD00 Figure 7 6 Timer Mode Control Register MCNTm Format 2 2 SMCLm2 SMCLm1 SMCLm0 Timer counter 1 clock selection 0 0 0 fR 0 0 1 fR 2 0 1 0 fR 16 0 1 1 fR 32 1 0 0 fR 64 1 0 1 fR 128 1 1 0 fR 256 1 1 1 fR 512 ...

Page 122: ...isabled by the PCEm bit of the timer mode control register The MCNTm register is cleared by MTRESET 0 or PCEm 0 and counting operation stops The first count cycle could include a clock error 1 fMCn clock due to the fact of the synchronization with the fMCn clock Figure 7 7 Restart Timing after Counting Operation Stopped Remark Counting operation starts counting operation stops counting operation s...

Page 123: ...t addition non addition to PWM output alternately upon MCNTm over flow output and enables the state of PWM output between current compare value N and the next com pare value N 1 Figure 7 8 Operation of 1 bit Addition Remark n 1 to 6 m 0 1 FFH 01H 00H PWM output of expected value N with 1 bit addition PWM output of expected value N without 1 bit addition Match signal of expected value N OVF0 OVF1 O...

Page 124: ...the rising edge of the output pin by 1 count clock of the MCNTm counter This shifted outputs prevent high current peaks that leads to VDD GND fluctuating Figure 7 9 Output Timing of SM11 to SM44 Figure 7 10 Output Timing of SM51 to SM64 MCNT0 Meter1 sin SM11 SM12 Meter2 sin SM21 SM22 Meter3 sin SM31 SM32 Meter4 sin SM41 SM42 Meter1 cos SM13 SM14 Meter2 cos SM23 SM24 Meter3 cos SM33 SM34 Meter4 cos...

Page 125: ...n0 1 bits by setting compare mode control register MCMPCn 5 Set PCE0 1 1 the counting operation timing with the specified counting selection starts 6 Ensure that TENn 0 rewriting period longer than count period until overflow 7 Rewrite compare register MCMPn0 MCMPn1 8 Set TENn 1 ADBn1 ADBn0 DIRn1 DIRn0 can be written at the same time if necessary MCMPn0 setting value MCMPn1 setting value FFH MCNTm...

Page 126: ...DIRn1 0 DIRn0 0 1 PCEm 1 is written counting operation starts 2 Overflow occurs 3 MCMPn0 or MCMPn1 match with setting value 4 CAE 0 and PCEm 0 are written counting value is cleared operation stops PWM output is disabled 5 MCMPn0 or MCMPn1 is rewritten 6 CAE 1 and PCEm 1 are written counting operation starts 7 TENn 1 is written ADBn1 ADBn0 DIRn1 DIRn0 bits can be written at the same time if necessa...

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Page 128: ...RC SFRs would be re initialized with a totally new transmis sion of the CSIB1 again Therefore the communication will be left out of synchroniza tion 2 During a Power save mode the signal at MTRESET pin should be high to remain the MTRC in operation mode but switched off Ring Oscillator Otherwise the MTRC will consume in reset mode more current via the PU PD resistors at the internal connection pin...

Page 129: ...elay between MTVDD apply and MTRESET release to ensure the minimum specified time between this points of time If the FG2 will be reset via an internal LVI or WD or external function RESET the PXX port will be set into its reset mode input but the pull up resistor RPU will hold the MTRC in its normal operation mode Therefore the last configured action PWM signal will remain It has to be checked if ...

Page 130: ...o 0 3 V SMVSS1 2 VSS EVSS BVSS AVSS MTVSS SMVSS 0 3 to 0 3 V AVSS VSS EVSS BVSS AVSS MTVSS SMVSS 0 3 to 0 3 V Input voltage VI1 P00 P06 P10 P11 P30 P39 P40 P42 P50 P55 P90 P96 P910 P915 RESET FLMD0 0 3 to EVDD 0 3a V VI2 PCM2 PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDL0 PDL13 0 3 to BVDD 0 3a V VI3 X1 X2 XT1 XT2 0 3 to VRO b 0 3a V VI4 PMT00 PMT03 PMT30 PMT35 PMT40 PMT43 MTRESET 0 3 to MTVDD 0 3a V Ana...

Page 131: ...stics and AC characteris tics represent the quality assurance range during normal operation Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of port pins Low level output current IOL P00 P06 P10 P11 P30 P39 P40 P42 P50 P55 P90 P96 P910 P915 1 pin 4 mA Total 50 mA P70 P715 1 pin 4 mA Total 20 mA PCM2 PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDL0 PDL13...

Page 132: ...MT30 PMT37 PMT40 PMT43 15 pF Output capacitance CO f 1 MHz Other than unmeasured pins 0 V Other than following pins 15 pF CSMO f 1 MHz Other than unmeasured pins 0 V PMT10 PMT17 PMT20 PMT27 SM11 SM14 SM21 SM24 40 pF Parameter Symbol Conditions MIN TYP MAX Unit Internal system clock frequency fCLK VDD 5 V 10 PLL mode OSC 4 MHz to 5 MHz 16 20 MHz VDD 4 0 to 5 5 V PLL mode OSC 4 MHz 16 16 16 MHz VDD ...

Page 133: ...r the same potential as VSS Do not ground the capacitor to a ground pattern through which a high cur rent flows Do not fetch signals from the oscillator 1 When the main clock is stopped and the device is operating on the subclock wait until the oscillation stabilization time has been secured by the program before switching back to the main clock Resonator Recommended circuit Parameter Conditions M...

Page 134: ...ground the capacitor to a ground pattern through which a high cur rent flows Do not fetch signals from the oscillator 1 The subclock oscillator is designed as a low amplitude circuit for reducing cur rent consumption and is more prone to malfunction due to noise than the main clock oscillator Particular care is therefore required with the wiring method when the subclock is used Resonator Recommend...

Page 135: ...Parameter Conditions MIN TYP MAX Unit Ring Oscillator Oscillation frequency fXR a a if calibration routine was successfully performed 6 8b b 4 MHz if uncalibrated 8 9 2 MHz Oscillation stabilization timec c time required when MRON bit is set from 0 to 1 20 us calibration pulse Calibration high pulsed d has to be exact the typ value 14 us calibration low pulse 3 us MTCS High Level width 600 ns Low ...

Page 136: ...acteristics VDD EVDD BVDD MTVDD SMVDD AVREF0 4 0 to 5 5 V VSS EVSS BVSS MTVSS SMVSS AVSS 0 V TA 40 to 85 C Parameter Symbol Conditions MIN TYP MAX Unit Input voltage VDD 3 5 5 5 V Output voltage VRO 2 5 V Lock time tREG After VDD reaches MIN 3 5 V Connect C 4 7 µF 20 to REGC pin 1 ms VDD 3 5 V VRO RESET tREG ...

Page 137: ...P06 P10 P11 P31 P33 P35 P39 P40 P42 P50 P55 P90 P96 P910 P912 P915 EVSS 0 2 EVDD V VIL3 PCM2 PCM3 PCS0 PCS1 PCT0 PCT1 PCT4 PCT6 PDL0 PDL13 BVSS 0 3 BVDD V VIL4 P70 P715 AVSS 0 3 AVREF0 V VIL5 RESET FLMD0 EVSS 0 2 EVDD V VIL6 PMT40 MTRESET MTVSS 0 2 MTVDD V VIL7 PMT00 PMT03 PMT30 PMT35 PMT41 PMT43 MTVSS 0 3 MTVDD V Output voltage high VOH1 a P00 P06 P10 P11 P30 P39 P40 P42 P50 P55 P90 P96 P910 P915...

Page 138: ... 21 mA TA 25 C IOH 28 mA TA 40 C 0 07 0 5 V VOL5 h PMT00 PMT03 PMT30 PMT35 PMT40 PMT43 IOL 1 0 mA 0 0 4 V Pull up resistor R1 VI 0 V 10 30 100 KΩ Pull down resistori R2 VI VDD 10 30 100 KΩ a Total IOH Max is 20 mA b IOL max of VOL3 is 16 mA c IOH max of VOH4 is 135 mA d IOH max of VOH5 is 12 mA e IOL max of VOL3 is 20 mA f IOL max of VOL3 is 16 mA g IOL max of VOL4 is 135 mA h IOL max of VOL5 is 1...

Page 139: ...On 20 5 33 mA All peripherals stopped MTRC Ring Oscillator On 11 mA Supply currentNote 1 IDD3 IDLE1 mode fXX 5 MHz OSC 5 MHz PLL On MTRC Ring Oscillator Off 0 6 0 92 mA IDD4 IDLE2 mode fXX 5 MHz OSC 5 MHz PLL Off MTRC Ring Oscillator Off 0 25 0 72 mA IDD5 Sub Operation modeb b Main Oscillator is off and Ring Oscillator is on Crystal resonator fXT 32 768 kHz RC resonatorc fXT 40 kHz MTRC Ring Oscil...

Page 140: ...t IDDDR VDDDR 2 0 V 6 65 µA Supply voltage rise time tRVD 1 µs Supply voltage fall time tFVD 1 µs Supply voltage retention time tHVD After STOP mode release 0 ms STOP release signal input time tDREL After VDD reaches MIN 3 5 V 0 µs Data retention input voltage high VIHDR All input ports 0 9VDDDR VDDDR V Data retention input voltage low VILDR All input ports 0 0 1VDDDR V tDREL tHVD tFVD tRVD STOP r...

Page 141: ...st Output Measurement Points Load Conditions Caution If the load capacitance exceeds 50 pF due to the circuit configuration bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means VDD VSS VIH MIN VIL MAX VIH MIN VIL MAX Measurement points VOH MIN VOL MAX VOH MIN VOL MAX Measurement points DUT Device under measurement CL 50 pF ...

Page 142: ...TVDD SMVDD AVREF0 4 0 to 5 5 V VSS EVSS BVSS MTVSS SMVSS AVSS 0 V TA 40 to 85 C CL 50 pF Clock Timing Parameter Symbol Conditions MIN MAX Unit Output cycle tCYK 62 5 ns 8 µs High level width tWKH tCYK 2 15 ns Low level width tWKL tCYK 2 15 ns Rising time tKR 15 ns Falling time tKF 15 ns CLKOUT output tCYK tWKH tWKL tKR tKF ...

Page 143: ... Conditions MIN MAX Unit RESET low level width tWRSL 500 ns NMI high level width tWNIH Analog noise elimination 500 ns NMI low level width tWNIL Analog noise elimination 500 ns INTPn high level widtha a ADTRG is same spec P03 INTP0 ADTRG DRST is same spec P05 INTP2 DRST tWITH Analog noise elimination n 0 to 7 500 ns Digital noise elimination n 3 b b 2Tsamp 20 or 3Tsamp 20 ns INTPn low level widtha...

Page 144: ... 50 pF Note 2Tsamp 20 or 3Tsamp 20 Tsamp Sampling clock for noise elimination Remark TIn TIP00 TIP01 TIP10 TIP11 TIP20 TIP21 TIP30 TIP31 TIQ00 to TIQ03 TIQ10 to TIQ13 Parameter Symbol Conditions MIN MAX Unit KRn input high level width tWKRH Analog noise elimination n 0 to 7 500 ns KRn input low level width tWKRL 500 ns Parameter Symbol Conditions MIN MAX Unit TIn high level width tTIH TIP00 TIP01 ...

Page 145: ...KCY0 125 ns SCKB0 high level width tKH0 tKCY0 2 15 ns SCKB0 low level width tKL0 tKCY0 2 15 ns SIB0 setup time to SCKB0 tSIK0 30 ns SIB0 hold time from SCKB0 tKSI0 25 ns SCKB0 to SOB0 output delay time tKSO0 25 ns Parameter Symbol Conditions MIN MAX Unit SCKB0 cycle time tKCY0 200 ns SCKB0 high level width tKH0 90 ns SCKB0 low level width tKL0 90 ns SIB0 setup time to SCKB0 tSIK0 50 ns SIB0 hold t...

Page 146: ...r Symbol Conditions MIN MAX Unit EXSCK1 cycle time tKCY1 250 1000a a Be sure to set cycle time EXSCK1 over 4 times as the internal system clock cycle 1 fCLK tKCY1 1 fCLK 4 If the CSI1 communicate with the uncalibrated MTRC fRO_uncal min 4 MHz tKCY1 has to be 1000 ns ns EXSCK1 high level width tKH1 tKCY1 2 30 ns EXSCK1 low level width tKL1 tKCY1 2 30 ns EXSI1 setup time to EXSCK1 tSIK1 50 ns EXSI1 ...

Page 147: ...AN CAN baud rate clock Remark n 0 1 Parameter Symbol Conditions MIN MAX Unit Transfer rate 1 Mbps Internal delay timea a Internal delay time tNODE Internal transfer delay time tOUTPUT Internal receive delay time tINPUT 100 ns CAN internal clock Note CTXDn pin Transfer data CRXDn pin Receive data tinput toutput V850ES FG2 CAN macro Image figure of internal delay CRXDn pin Internal receive delay Int...

Page 148: ...version time tCONV 3 1 16 µ s Analog input voltage VIAN AVSS AVREF0 V AVREF0 current IAREF0 When using A D converter 5 10 mA When not using A D converter 1 10 µ A Parameter Symbol Conditions MIN TYP MAX Unit Detection voltage VLVI0 4 2 4 4 4 6 V VLVI1 4 0 4 2 4 4 V Response timea a The time required to output an interrupt reset after the detection voltage is detected tLD After VDD reaches VLVI0 VL...

Page 149: ...IN TYP MAX Unit Detection voltage VRAMH 1 9 2 0 2 1 V Supply voltage rise time tRAMHTH VDD 0 V 3 5 V 0 002 1 800 ms Response timea a Time required to set the RAMF bit after the detection voltage is detected tRAMHD After the supply voltage reaches the detection volt age MAX 0 2 2 0 ms Minimum VDD width tRAMHW 0 2 ms tRAMHD VDD Detection voltage MAX Detection voltage TYP Detection voltage MIN Operat...

Page 150: ...ber of writes CWRT a a The initial write when the product is shipped any erase write set of operations or any programming operation is counted as one rewrite 100 Times Input voltage high VIH FLMD0 0 8EVDD EVDD V Input voltage low VIL FLMD0 EVSS 0 2EVDD V Programming temperature tPRG 40 85 C Parameter Symbol Conditions MIN TYP MAX Unit FLMD0 setup time from RESET tRFCF 5000 fX α s Count execution t...

Page 151: ...151 Chapter 9 Electrical Specification Preliminary User s Manual U17763EE1V1UD00 MEMO ...

Page 152: ...ITEM MILLIMETERS NOTE A 22 0 0 2 B 20 0 0 2 C 20 0 0 2 D F 1 25 22 0 0 2 S144GJ 50 UEN S 1 5 0 1 K 1 0 0 2 L 0 5 0 2 R 3 4 3 G 1 25 H 0 22 0 05 I 0 08 J 0 5 T P M 0 17 N 0 08 P 1 4 Q 0 10 0 05 0 03 0 07 Each lead centerline is located within 0 08 mm of its true position T P at maximum material condition S S M detail of lead end I J F G H Q R P K M L N C D S A B ...

Page 153: ...153 Preliminary User s Manual U17763EE1V1UD00 MEMO ...

Page 154: ...formation document Semiconductor Device Mounting Technology Manual C10535E For soldering methods and conditions other than those recommended please consult NEC Caution Do not use two or more soldering methods in combination except partial heating method Soldering Method Soldering Condition Symbol of Recommended Soldering Condition Infrared reflow Package peak temperature 235 C IR35 207 3 Partial h...

Page 155: ...155 Preliminary User s Manual U17763EE1V1UD00 MEMO ...

Page 156: ...156 Chapter 11 Recommended Soldering Conditions Preliminary User s Manual U17763EE1V1UD00 ...

Page 157: ...ock generator 39 Clock Monitor 59 Compare control register 118 Cos Compare Register n1 117 CSIB 52 D DMA Controller 55 DMAC 55 F Flash Memory 62 Free running counter m 115 I Interrupt Controller 54 K Key Interrupt 56 L Low voltage Detector 60 M MCMPCn 118 MCMPn0 116 MCMPn1 117 MCNTm 115 120 MRCTL 93 95 O On chip debug 64 P PMCMT1 82 PMCMT2 86 PMCMT4 91 PMMT0 79 ...

Page 158: ... 90 Port MT0 Mode Register 0 79 Port Register 0 79 Port Register 1 81 Port Register 2 85 Port Register 3 88 Port Register 4 90 R RingOSC Control Register for the Meter 93 95 ROM Mask Options Function 63 S Sin Compare Register n0 116 SM12MC 83 SM1SM2 Mode Control Register 83 Standby 57 T Timer M 45 Timer Mode Control Register 120 Timer P 41 Timer Q 43 U UARTA 50 V V850ES FG2 block diagram 27 V850ES...

Page 159: ...ronics Taiwan Ltd Fax 02 2719 5951 Address North America NEC Electronics America Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 0 211 6503 1344 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 6250 3583 Japan NEC Semiconductor Technical Hotline I would like to report the following erro...

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