NEC PD78056F User Manual Download Page 434

Page: 434 / 593

434

CHAPTER 19 SERIAL INTERFACE CHANNEL 2

19.2 Serial Interface Channel 2 Configuration

Serial interface channel 2 consists of the following hardware.

Table 19-1. Serial Interface Channel 2 Configuration

Item

Configuration

Transmit shift register (TXS)

Receive shift register (RXS)

Receive buffer register (RXB)

Control register

Serial operating mode register 2 (CSIM2)

Asynchronous serial interface mode register (ASIM)

Asynchronous serial interface status register (ASIS)

Baud rate generator control register (BRGC)

Port Mode Register 7 (PM7)

Note

See Figure 6-15 P70 Block Diagram and Figure 6-16 P71 and P72 Block Diagram.

Summary of Contents for PD78056F

Page 1: ... µPD78058F 78058FY Subseries 8 Bit Single Chip Microcontrollers µPD78056F µPD78058F µPD78P058F µPD78058F A µPD78056FY µPD78058FY µPD78P058FY µPD78058FY A Document No U12068EJ2V0UM00 2nd edition Date Published April 1998 N CP K 1997 ...

Page 2: ...2 MEMO ...

Page 3: ...ch unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does no...

Page 4: ...ility of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customers must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grad...

Page 5: ...e Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Spain Office Madrid Spain Tel 01 504 2787 Fax 01 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 Regional Information Some information contained in this document may vary from cou...

Page 6: ...e 16 5 Serial Bus Interface Control Register Format was changed P308 Cautions were added to 16 4 3 2 a Bus release signal REL and b Command signal CMD P435 P436 CSCK was deleted from Figure 19 1 Serial Interface Channel 2 Block Diagram and Figure 19 2 Baud Rate Generator Block Diagram P438 Figure 19 3 Serial Operating Mode Register 2 Format was changed P440 Table 19 2 Serial Interface Channel 2 Op...

Page 7: ...Subseries µPD78056FY 78058FY 78P058FY 78058FY A Purpose This manual is intended for users to understand the functions described in the Organization below Organization The µPD78058F 78058FY Subseries manual is organized by two volumes this manual and the instruction edition common to the 78K 0 Series µPD78058F 78058FY 78K 0 Series Subseries User s Manual User s Manual Instructions This Manual Pin f...

Page 8: ... How to interpret the register format For the circled bit number the bit name is defined as a reserved word in RA78K 0 and in CC78K 0 already defined in the header file named sfrbit h To learn the function of a register whose register name is known Refer to APPENDIX D REGISTER INDEX To know the electrical specifications of the µPD78058F and 78058FY Subseries Refer to separately available Data Shee...

Page 9: ...16 Bit Timer Event Counter Chapter 9 8 Bit Timer Event Counter Chapter 10 Watch Timer Chapter 11 Watchdog Timer Chapter 12 Clock Output Control Circuit Chapter 13 Buzzer Output Control Circuit Chapter 14 A D Converter Chapter 15 D A Converter Chapter 16 Serial Interface Channel 0 µPD78058F Subseries Chapter 17 Serial Interface Channel 0 µPD78058FY Subseries Chapter 18 Serial Interface Channel 1 Ch...

Page 10: ...wire serial I O mode 2 wire serial I O mode SBI serialbusinterface mode I2 C bus mode Supported Not supported Conventions Data significance Higher digits on the left and lower digits on the right Active low representations overscore over pin or signal names Note Footnotes for item marked with Note in the text Caution Information requiring particular attention Remarks Supplementary information Nume...

Page 11: ...326E 78K 0 Series Instruction Table U10903J 78K 0 Series Instruction Set U10904J 78K 0 Series Application Note Basic III U10182J U10182E Related Documents for µPD78058FY Subseries Document Name Document No Japanese English µPD78056FY 78058FY Data Sheet U12142J U12142E µPD78P058FY Data Sheet U12076J U12076E µPD78058F 78058FY Subseries User s Manual U12068J This manual 78K 0 Series User s Manual Ins...

Page 12: ... IBM PC Series PC DOS Base EEU 5008 U10540E IE 78K0 NS To be prepared To be prepared IE 78001 R A To be prepared To be prepared IE 780308 NS EM1 To be prepared To be prepared IE 78064 R EM EEU 905 EEU 1443 IE 780308 R EM U11362J U11362E EP 78230 EEU 985 EEU 1515 EP 78054GK R EEU 932 EEU 1468 SM78K0 System Simulator Windows Base Reference U10181J U10181E SM78K Series System Simulator External compo...

Page 13: ... Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliability Quality Control on NEC Semiconductor Devices C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892E Guide to Quality Assurance for Semiconductor Devices MEI 1202 Microcontroller Related Product Guide Third Party Manufacturers U...

Page 14: ...14 MEMO ...

Page 15: ... 50 2 6 78K 0 Series Expansion 53 2 7 Block Diagram 55 2 8 Outline of Function 56 2 9 Differences Between the µPD78058FY and µPD78058FY A 57 2 10 Mask Options 58 CHAPTER 3 PIN FUNCTION µPD78058F SUBSERIES 59 3 1 Pin Function List 59 3 1 1 Normal operating mode pins 59 3 1 2 PROM programming mode pins PROM versions only 64 3 2 Description of Pin Functions 65 3 2 1 P00 to P07 Port 0 65 3 2 2 P10 to ...

Page 16: ...o P37 Port 3 85 4 2 5 P40 to P47 Port 4 86 4 2 6 P50 to P57 Port 5 86 4 2 7 P60 to P67 Port 6 86 4 2 8 P70 to P72 Port 7 87 4 2 9 P120 to P127 Port 12 88 4 2 10 P130 and P131 Port 13 88 4 2 11 AVREF0 88 4 2 12 AVREF1 88 4 2 13 AVDD 89 4 2 14 AVSS 89 4 2 15 RESET 89 4 2 16 X1 and X2 89 4 2 17 XT1 and XT2 89 4 2 18 VDD 89 4 2 19 VSS 89 4 2 20 VPP PROM versions only 89 4 2 21 IC Mask ROM version only...

Page 17: ...4 9 Stack addressing 124 CHAPTER 6 PORT FUNCTIONS 125 6 1 Port Functions 125 6 2 Port Configuration 130 6 2 1 Port 0 130 6 2 2 Port 1 132 6 2 3 Port 2 µPD78058F Subseries 133 6 2 4 Port 2 µPD78058FY Subseries 135 6 2 5 Port 3 137 6 2 6 Port 4 138 6 2 7 Port 5 139 6 2 8 Port 6 140 6 2 9 Port 7 142 6 2 10 Port 12 144 6 2 11 Port 13 145 6 3 Port Function Control Registers 146 6 4 Port Function Operat...

Page 18: ...tput operations 189 8 5 3 PPG output operation 192 8 5 4 Pulse width measurement operations 193 8 5 5 External event counter operation 200 8 5 6 Square wave output operation 202 8 5 7 One shot pulse output operation 204 8 6 16 Bit Timer Event Counter Operating Precautions 208 CHAPTER 9 8 BIT TIMER EVENT COUNTERS 211 9 1 8 Bit Timer Event Counter Function 211 9 1 1 8 bit timer event counter mode 21...

Page 19: ...R 261 14 1 A D Converter Functions 261 14 2 A D Converter Configuration 262 14 3 A D Converter Control Registers 265 14 4 A D Converter Operations 269 14 4 1 Basic operations of A D converter 269 14 4 2 Input voltage and conversion results 271 14 4 3 A D converter operating mode 272 14 5 A D Converter Cautions 274 CHAPTER 15 D A CONVERTER 279 15 1 D A Converter Functions 279 15 2 D A Converter Con...

Page 20: ...18 2 Serial Interface Channel 1 Configuration 388 18 3 Serial Interface Channel 1 Control Registers 391 18 4 Serial Interface Channel 1 Operations 399 18 4 1 Operation stop mode 399 18 4 2 3 wire serial I O mode operation 400 18 4 3 3 wire serial I O mode operation with automatic transmit receive function 403 CHAPTER 19 SERIAL INTERFACE CHANNEL 2 433 19 1 Serial Interface Channel 2 Functions 433 1...

Page 21: ...l Register 508 22 3 External Device Expansion Function Timing 510 CHAPTER 23 STANDBY FUNCTION 515 23 1 Standby Function and Configuration 515 23 1 1 Standby function 515 23 1 2 Standby function control register 516 23 2 Standby Function Operations 517 23 2 1 HALT mode 517 23 2 2 STOP mode 520 CHAPTER 24 RESET FUNCTION 523 24 1 Reset Function 523 CHAPTER 25 ROM CORRECTION 527 25 1 ROM Correction Fu...

Page 22: ...ed by Addressing Type 560 APPENDIX A DIFFERENCES AMONG µPD78054 78058F AND 780058 SUBSERIES 565 APPENDIX B DEVELOPMENT TOOLS 567 B 1 Language Processing Software 570 B 2 PROM Programming Tool 571 B 2 1 Hardware 571 B 2 2 Software 571 B 3 Debugging Tool 572 B 3 1 Hardware 572 B 3 2 Software 574 B 4 OS for IBM PC 576 B 5 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A 576 APPE...

Page 23: ...o P06 Block Diagram 131 6 4 P10 to P17 Block Diagram 132 6 5 P20 P21 P23 to P26 Block Diagram 133 6 6 P22 and P27 Block Diagram 134 6 7 P20 P21 P23 to P26 Block Diagram 135 6 8 P22 and P27 Block Diagram 136 6 9 P30 to P37 Block Diagram 137 6 10 P40 to P47 Block Diagram 138 6 11 Block Diagram of Falling Edge Detection Circuit 138 6 12 P50 to P57 Block Diagram 139 6 13 P60 to P63 Block Diagram 141 6...

Page 24: ...r Application Circuit Example 191 8 16 Control Register Settings for PPG Output Operation 192 8 17 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register 193 8 18 Configuration Diagram for Pulse Width Measurement by Free Running Counter 194 8 19 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both E...

Page 25: ...t Control Register Format 223 9 7 Port Mode Register 3 Format 224 9 8 Interval Timer Operation Timings 225 9 9 External Event Counter Operation Timings with Rising Edge Specified 228 9 10 Square Wave Output Operation Timing 230 9 11 Interval Timer Operation Timing 231 9 12 External Event Counter Operation Timings with Rising Edge Specified 233 9 13 Square Wave Output Operation Timing 235 9 14 8 Bi...

Page 26: ... 284 16 1 Serial Bus Interface SBI System Configuration Example 287 16 2 Serial Interface Channel 0 Block Diagram 289 16 3 Timer Clock Select Register 3 Format 293 16 4 Serial Operating Mode Register 0 Format 294 16 5 Serial Bus Interface Control Register Format 296 16 6 Interrupt Timing Specify Register Format 298 16 7 3 Wire Serial I O Mode Timings 303 16 8 RELT and CMDT Operations 303 16 9 Circ...

Page 27: ...n Transfer Bit Order 357 17 10 Serial Bus Configuration Example Using 2 Wire Serial I O Mode 358 17 11 2 Wire Serial I O Mode Timings 361 17 12 RELT and CMDT Operations 362 17 13 Example of Serial Bus Configuration Using I2 C Bus 363 17 14 I2 C Bus Serial Data Transfer Timing 364 17 15 Start Condition 365 17 16 Address 365 17 17 Transfer Direction Specification 365 17 18 Acknowledge Signal 366 17 ...

Page 28: ...the Bit Slippage Detection Function Through the Busy Signal When BUSY0 1 428 18 23 Automatic Transmit Receive Interval Time 429 18 24 Operation Timing with Automatic Data Transmit Receive Function Performed by Internal Clock 430 19 1 Serial Interface Channel 2 Block Diagram 435 19 2 Baud Rate Generator Block Diagram 436 19 3 Serial Operating Mode Register 2 Format 438 19 4 Asynchronous Serial Inte...

Page 29: ...inimum Time 496 21 15 Interrupt Request Acknowledge Timing Maximum Time 496 21 16 Multiple Interrupt Example 499 21 17 Interrupt Request Hold 501 21 18 Basic Configuration of Test Function 502 21 19 Format of Interrupt Request Flag Register 1L 503 21 20 Format of Interrupt Mask Flag Register 1L 503 21 21 Key Return Mode Register Format 504 22 1 Memory Map When Using External Device Expansion Funct...

Page 30: ...hen One Place Is Corrected 534 25 10 Program Transition Diagram When Two Places Are Corrected 535 26 1 Memory Size Switching Register Format 538 26 2 Internal Expansion RAM Size Switching Register Format 539 26 3 Page Program Mode Flowchart 542 26 4 Page Program Mode Timing 543 26 5 Byte Program Mode Flowchart 544 26 6 Byte Program Mode Timing 545 26 7 PROM Read Timing 546 B 1 Development Tool Con...

Page 31: ...er 168 8 1 Timer Event Counter Operation 172 8 2 16 Bit Timer Event Counter Interval Times 173 8 3 16 Bit Timer Event Counter Square Wave Output Ranges 174 8 4 16 Bit Timer Event Counter Configuration 174 8 5 INTP0 TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge 177 8 6 16 Bit Timer Event Counter Interval Times 189 8 7 16 Bit Timer Event Count Square Wave Output Ranges 203 9 1 8 Bit Timer ...

Page 32: ...16 3 Various Signals in SBI Mode 321 17 1 Differences Among Channels 0 1 and 2 337 17 2 Serial Interface Channel 0 Configuration 340 17 3 Serial Interface Channel 0 Interrupt Request Signal Generation 344 17 4 Signals in I2 C Bus Mode 371 18 1 Serial Interface Channel 1 Configuration 388 18 2 Interval Timing Through CPU Processing When the Internal Clock Is Operating 430 18 3 Interval Timing Throu...

Page 33: ...in External Memory Expansion Mode 505 22 3 Values When the Memory Size Switching Register Is Reset 509 23 1 HALT Mode Operating Status 517 23 2 Operation After HALT Mode Release 519 23 3 STOP Mode Operating Status 520 23 4 Operation After STOP Mode Release 522 24 1 Hardware Status After Reset 525 25 1 ROM Correction Configuration 527 26 1 Differences Between µPD78P058F 78P058FY and Mask ROM Versio...

Page 34: ...34 MEMO ...

Page 35: ...ansion Space 64 Kbytes Minimum instruction execution time changeable from high speed 0 4 µs In main system clock 5 0 MHz operation to ultra low speed 122 µs In subsystem clock 32 768 kHz operation Instruction set suited to system control Bit manipulation possible in all address spaces Multiply and divide instructions 69 I O ports 4 N ch open drain ports 8 bit resolution A D converter 8 channels 8 ...

Page 36: ...0 pin plastic QFP 14 14 mm Resin thickness 2 7 mm Mask ROM µPD78056FGC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Mask ROM µPD78058FGC 3B9 80 pin plastic QFP 14 14 mm Resin thickness 2 7 mm Mask ROM µPD78058FGC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Mask ROM µPD78058FGK BE9 80 pin plastic TQFP Fine pitch 12 12 mm Mask ROM µPD78058FGC A 3B9 80 pin plastic QFP 14 14 mm Re...

Page 37: ...m Resin thickness 1 4 mm Standard µPD78058FGK BE9 80 pin plastic TQFP Fine pitch 12 12 mm Standard µPD78058FGC A 3B9 80 pin plastic QFP 14 14 mm Resin thickness 2 7 mm Special µPD78P058FGC 3B9 80 pin plastic QFP 14 14 mm Resin thickness 2 7 mm Standard µPD78P058FGC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Standard Remark indicates ROM code suffix Please refer to Quality grade on NEC ...

Page 38: ...e generated internally in the microprocessor is required please connect it to a ground line which is separate from VSS Remark Pin connection in parentheses is intended for the µPD78P058F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P15 ANI5 P16 ANI6 P17 ANI7 AVSS P130 ANO0 P131 ANO1 AVREF1 P70 SI2 RxD P71 SO2 TxD P72 SCK2 ASCK P20 S...

Page 39: ...rt0 P10 to P17 Port1 P20 to P27 Port2 P30 to P37 Port3 P40 to P47 Port4 P50 to P57 Port5 P60 to P67 Port6 P70 to P72 Port7 P120 to P127 Port12 P130 P131 Port13 PCL Programmable Clock RD Read Strobe RESET Reset RTP0 to RTP7 Real Time Output Port RxD Receive Data SB0 SB1 Serial Bus SCK0 to SCK2 Serial Clock SI0 to SI2 Serial Input SO0 to SO2 Serial Output STB Strobe TI00 TI01 Timer Input TI1 TI2 Tim...

Page 40: ...thing A0 to A16 Address Bus RESET Reset CE Chip Enable VDD Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground PGM Program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS RESET D7 D6 D5 D4 D3 D2 D1 D0 CE V SS V DD L Open V PP L Open V DD PGM L A9 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A12 A13 V SS A14 ...

Page 41: ... chip UART capable of operation at a low voltage 1 8 V I O and FIP C D of the PD78044F were enhanced Display output total 53 I O and FIP C D of the PD78044H were enhanced Display output total 48 N ch open drain I O was added to the PD78044F Display output total 34 PD780988 64 pin 64 pin Inverter control The inverter control timer and SIO of the PD780964 were enhanced ROM size and RAM size were exp...

Page 42: ... 8 K to 32 K 2 7 V µPD780001 8 K 1 ch 39 µPD78002 8 K to 16 K 1 ch 53 µPD78083 8 ch 1 ch UART 1 ch 33 1 8 V Inverter µPD780988 32 K to 60 K 3 ch Note 1 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V control µPD780964 8 K to 32 K Note 2 2 ch UART 2 ch 2 7 V µPD780924 8 ch FIP µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V drive µPD780228 48 K to 60 K 3 ch 1 ch 72 4 5 V µPD78044H 32 K to 48 K 2 ch...

Page 43: ...PU CORE ROM RAM PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 12 PORT 13 REAL TIME OUTPUT PORT EXTERNAL ACCESS SYSTEM CONTROL P00 P01 to P06 P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 RTP0 P120 to RTP7 P127 AD0 P40 to AD7 P47 A8 P50 to A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET X1 X2 XT1 P07 XT2 TO0 P30 TI00 INTP0 P00 T...

Page 44: ...erial interface 3 wire serial I O SBI 2 wire serial I O mode selection possible 1 channel 3 wire serial I O mode Max 32 byte on chip auto transmit receive 1 channel 3 wire serial I O UART mode selectable 1 channel Timer 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output Three outputs 14 bit PWM output enable 1 Clock...

Page 45: ...mm Resin thickness 2 7 mm 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm 80 pin plastic TQFP Fine pitch 12 12 mm µPD78058F only 1 9 Differences Between the µPD78058F and µPD78058F A Table 1 1 Differences Between the µPD78058F and µPD78058F A Item Part Number µPD78056F µPD78058F µPD78P058F Item Part Number µPD78058F µPD78058F A Quality grade Standard Special Package 80 pin Plastic QFP 80 pin Pl...

Page 46: ...ll up resistors shown in Table 1 2 incorporated on chip If a mask option is used when pull up resistors are required the number of parts can be reduced and package area can be shrunk The mask option provided for the µPD78058F Subseries is shown in Table 1 2 Table 1 2 Mask Options of Mask POM Versions Pin Names Mask Options P60 to P63 Pull up resistors can be incorporated in 1 bit units ...

Page 47: ...tion possible in all address spaces Multiply and divide instructions I O ports 69 N ch open drain ports 4 8 bit resolution A D converter 8 channels 8 bit resolution D A converter 2 channels Serial interface 3 channels 3 wire serial I O 2 wire serial I O I2C bus mode 1 channel 3 wire serial I O mode Automatic transmit receive function 1 channel 3 wire serial I O UART mode 1 channel Timer 5 channels...

Page 48: ...QFP 14 14 mm Resin thickness 2 7 mm Mask ROM µPD78056FYGC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Mask ROM µPD78058FYGC 3B9 80 pin plastic QFP 14 14 mm Resin thickness 2 7 mm Mask ROM µPD78058FYGC 8BT 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Mask ROM µPD78058FYGK BE9 80 pin plastic TQFP Fine pitch 12 12 mm Mask ROM µPD78058FYGC A 3B9 80 pin plastic QFP 14 14 mm Resin thick...

Page 49: ...ness 1 4 mm Standard µPD78058FYGK BE9 80 pin plastic TQFP Fine pitch 12 12 mm Standard µPD78058FYGC A 3B9 80 pin plastic QFP 14 14 mm Resin thickness 2 7 mm Special µPD78P058FYGC 3B9 80 pin plastic QFP 14 14 mm Resin thickness 2 7 mm Standard µPD78P058FYGC 8BTNote 80 pin plastic QFP 14 14 mm Resin thickness 1 4 mm Standard Note Under development Remark indicates ROM code suffix Please refer to Qua...

Page 50: ...V DD XT1 P07 XT2 IC V PP X1 X2 V DD P06 INTP6 P05 INTP5 P04 INTP4 P03 INTP3 P02 INTP2 P01 INTP1 TI01 P00 INTP0 TI00 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 P50 A8 P51 A9 P52 A10 P53 A11 P54 A12 P55 A13 V SS P56 A14 P57 A15 P60 P61 P62 P63 P64 RD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Note Under development Cau...

Page 51: ...t1 P20 to P27 Port2 P30 to P37 Port3 P40 to P47 Port4 P50 to P57 Port5 P60 to P67 Port6 P70 to P72 Port7 P120 to P127 Port12 P130 P131 Port13 PCL Programmable Clock RD Read Strobe RESET Reset RTP0 to RTP7 Real Time Output Port RxD Receive Data SB0 SB1 Serial Bus SCK0 to SCK2 Serial Clock SCL Serial Clock SDA0 SDA1 Serial Data SI0 to SI2 Serial Input SO0 to SO2 Serial Output STB Strobe TI00 TI01 Ti...

Page 52: ...not connect anything A0 to A16 Address Bus RESET Reset CE Chip Enable VDD Power Supply D0 to D7 Data Bus VPP Programming Power Supply OE Output Enable VSS Ground PGM Program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS RESET D7 D6 D5 D4 D3 D2 D1 D0 CE V SS V DD L Open V PP L Open V DD PGM L A9 A2 A3 A4 A5 A6 A7 A8 A16 A10 A11 A1...

Page 53: ...UART capable of operation at a low voltage 1 8 V The I O and FIP C D of the PD78044F were enhanced Display output total 53 The I O and FIP C D of the PD78044H were enhanced Display output total 48 N ch open drain I O was added to the PD78044F Display output total 34 PD780988 64 pin 64 pin Inverter control The inverter control timer and SIO of the PD780964 were enhanced ROM size and RAM size were e...

Page 54: ...Time division UART 1 ch µPD78058FY 48 K to 60 K 3 wire 2 wire I2C 1 ch 69 2 7 V µPD78054Y 16 K to 60 K 3 wire with automatic send receive function 1 ch 2 0 V 3 wire UART 1 ch µPD780034Y 8 K to 32 K UART 1 ch 51 1 8 V µPD780024Y 3 wire 1 ch I2C Bus Multi Master compatible 1 ch µPD78018FY 8 K to 60 K 3 wire 2 wire I2C 1 ch 53 3 wire with automatic send receive function 1 ch µPD78014Y 8 K to 32 K 3 w...

Page 55: ...OM RAM PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 12 PORT 13 REAL TIME OUTPUT PORT EXTERNAL ACCESS SYSTEM CONTROL P00 P01 to P06 P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P72 P120 to P127 P130 P131 RTP0 P120 to RTP7 P127 AD0 P40 to AD7 P47 A8 P50 to A15 P57 RD P64 WR P65 WAIT P66 ASTB P67 RESET X1 X2 XT1 P07 XT2 TO0 P30 TI00 INTP0 P00 TI01 INTP1...

Page 56: ...al I O I2C bus mode selection possible 1 channel 3 wire serial I O mode Max 32 byte on chip auto transmit receive 1 channel 3 wire serial I O UART mode selectable 1 channel Timer 16 bit timer event counter 1 channel 8 bit timer event counter 2 channels Watch timer 1 channel Watchdog timer 1 channel Timer output Three outputs 14 bit PWM output enable 1 Clock output 19 5 kHz 39 1 kHz 78 1 kHz 156 kH...

Page 57: ...mm Note 80 pin plastic TQFP Fine pitch 12 12 mm µPD78058FY only Note Under development for the µPD78P058FY only 2 9 Differences Between the µPD78058FY and µPD78058FY A Table 2 1 Differences Between the µPD78058FY and µPD78058FY A Item Part Number µPD78056FY µPD78058FY µPD78P058FY Item Part Number µPD78058FY µPD78P058FY A Quality grade Standard Special Package 80 pin Plastic QFP 80 pin Plastic QFP ...

Page 58: ...ort pin when the user places an order for the device production Using this mask option when pull up resistors are required reduces the number of components to add to the device resulting in board space saving The mask options provided in the µPD78058FY Subseries are shown in Table 2 2 Table 2 2 Mask Options of Mask ROM Versions Pin Names Mask Options P60 to P63 Pull up resistor connection can be s...

Page 59: ... be used by softwareNote 2 P20 Input Port 2 Input SI1 P21 output 8 bit input output port SO1 P22 Input output mode can be specified bit wise SCK1 P23 If used as an input port an on chip pull up resistor can be used by STB P24 software BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 Notes 1 When the P07 XT1 pin is used as an input port set the bit 6 FRC of the processor clock control register PCC to 1 do not...

Page 60: ...dge detection P50 to P57 Input Port 5 Input A8 to A15 output 8 bit input output port LED can be driven directly Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software P60 Input Port 6 Input P61 output 8 bit input output port P62 Input output mode can be P63 specified bit wise P64 If used as an input port an on chip RD P65 pull up re...

Page 61: ...t 13 Input ANO0 to ANO1 2 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software Cautions For pins which have alternate functions as port output do not execute the following operations during A D conversion If performed then the general error standards cannot be maintained during A D conversion 1 If it is used ...

Page 62: ...obe output Input P23 BUSY Input Serial interface automatic transmit receive busy input Input P24 RxD Input Asynchronous serial interface serial data input Input P70 SI2 TxD Output Asynchronous serial interface serial data output Input P71 SO2 ASCK Input Asynchronous serial interface serial clock input Input P72 SCK2 TI00 Input External count clock input to 16 bit timer TM0 Input P00 INTP0 TI01 Cap...

Page 63: ...ommon with the port s ground potential of the A D converter and D A converter RESET Input System reset input X1 Input Crystal connection for main system clock oscillation X2 XT1 Input Crystal connection for subsystem clock osicllation Input P07 XT2 VDD Positive power supply Except the port VPP High voltage application for program write verify Connect directly to VSS in the normal operation mode VS...

Page 64: ...ow level voltage is applied to the RESET pin the PROM programming mode is set VPP Input High voltage application for PROM programming mode setting and program write verify A0 to A16 Input Address bus D0 to D7 Input output Data bus CE Input PROM enable input program pulse input OE Input Read strobe input to PROM PGM Input Program program inhibit input in PROM programming mode VDD Positive power sup...

Page 65: ...hey are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation a INTP0 to INTP6 INTP0 to INTP6 are external interrupt request input pins which can ...

Page 66: ...7 Port 2 These are 8 bit input output ports Besides serving as input output ports they function as data input output to from the serial interface clock input output automatic transmit receive busy input and strobe output functions The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output po...

Page 67: ...ut output ports Beside serving as input output ports they function as timer input output clock output and buzzer output The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 3 PM3 When they are used as input ports on chip pull up resistors can be used by de...

Page 68: ...pull up resistor is automatically disabled 3 2 6 P50 to P57 Port 5 These are 8 bit input output ports Besides serving as input output ports they function as an address bus Port 5 can drive LEDs directly The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input output ports with port mode register 5 P...

Page 69: ...ion to its use as an input output port it also has serial interface data input output and clock input output functions The following operating modes can be specified bit wise 1 Port mode Port 7 functions as a 3 bit input output port Bit wise specification as an input port or output port is possible by means of port mode register 7 PM7 When used as input ports on chip pull up resistors can be used ...

Page 70: ...e following operating modes can be specified bit wise 1 Port mode These ports function as 2 bit input output ports They can be specified bit wise as input or output ports with port mode register 13 PM13 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports allow D A converter analog output ANO0 and...

Page 71: ...hat of the VSS pin 3 2 15 RESET This is a low level active system reset input pin 3 2 16 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to X1 and its inverted signal to X2 3 2 17 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation For external clock supply input it to XT1 and its inverted signal to XT2 3 2 18 VDD...

Page 72: ... at delivery Connect it directly to the VSS with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program may not run normally Connect IC pins to VSS pins directly VSS IC As short as possible ...

Page 73: ...VSS P21 SO1 5 J P22 SCK1 8 D P23 STB 5 J P24 BUSY 8 D P25 SI0 SB0 P26 SO0 SB1 10 C P27 SCK0 P30 TO0 5 J Input output P31 TO1 P32 TO2 P33 TI1 8 D P34 TI2 P35 PCL 5 J P36 BUZ P37 P40 AD0 to P47 AD7 5 O Input output Connect independently via a resistor to VDD P50 A8 to P57 A15 5 J Input output Connect independently via a resistor to VDD or VSS 3 3 Input output Circuits and Recommended Connection of U...

Page 74: ...output Connect independently via a resistor to VDD or VSS P65 WR P66 WAIT P67 ASTB P70 SI2 RxD 8 D P71 SO2 TxD 5 J P72 SCK2 ASCK 8 D P120 RTP0 to P127 RTP7 5 J P130 ANO0 P131 ANO1 12 B Input output Connect independently via a resistor to VSS RESET 2 Input XT2 16 Leave open AVREF0 Connect to VSS AVREF1 Connect to VDD AVDD Connect to a separate power supply with the same potential as VDD AVSS Connec...

Page 75: ...teresis Characteristics Type 5 O Type 11 C Type 10 C Type 8 D pull up enable AVDD P ch IN OUT output disable data AVDD P ch N ch pull up enable AVDD P ch IN OUT output disable data AVDD P ch N ch pull up enable AVDD P ch IN OUT open drain output disable data AVDD P ch N ch pull up enable AVDD P ch IN OUT output disable data AVDD P ch N ch P ch comparator AVSS input enable VREF Threshold voltage AV...

Page 76: ...t disable AVDD N ch IN OUT RD medium breakdown input buffer data P ch XT2 XT1 feedback cut off P ch Type 16 output disable AVDD AVDD N ch Mask Option IN OUT RD medium breakdown input buffer data P ch pullup enable AVDD P ch IN OUT output disable data AVDD P ch N ch input enable P ch N ch analog output voltage AVSS AVSS AVSS AVSS ...

Page 77: ...tput port Input output mode can be specified bit wise If used as input port an on chip pull up resistor can be used by softwareNote 2 P20 Input Port 2 Input SI1 P21 output 8 bit input output port SO1 P22 Input output mode can be specified bit wise SCK1 P23 If used as an input port an on chip pull up resistor can be used by STB P24 software BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL Notes ...

Page 78: ...ied in 8 bit units If used as an input port an on chip pull up resistor can be used by software Test input flag KRIF is set to 1 by falling edge detection P50 to P57 Input Port 5 Input A8 to A15 output 8 bit input output port LED can be driven directly Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software P60 Input Port 6 Input P61...

Page 79: ...ort 13 Input ANO0 to ANO1 output 2 bit input output port Input output mode can be specified bit wise If used as an input port an on chip pull up resistor can be used by software Cautions For pins which have alternate functions as port output do not execute the following operations during A D conversion If performed then the general error standards cannot be maintained during A D conversion 1 If it...

Page 80: ...rface automatic transmit receive strobe output Input P23 BUSY Input Serial interface automatic transmit receive busy input Input P24 RxD Input Asynchronous serial interface serial data input Input P70 SI2 TxD Output Asynchronous serial interface serial data output Input P71 SO2 ASCK Input Asynchronous serial interface serial clock input Input P72 SCK2 TI00 Input External count clock input to 16 bi...

Page 81: ...t power supply AVSS Ground potential common with the port s ground potential of the A D converter and D A converter RESET Input System reset input X1 Input Crystal connection for main system clock oscillation X2 XT1 Input Crystal connection for subsystem clock oscillation Input P07 XT2 VDD Positive power supply Except the port VPP High voltage application for program write verify Connect directly ...

Page 82: ...ow level voltage is applied to the RESET pin the PROM programming mode is set VPP Input High voltage application for PROM programming mode setting and program write verify A0 to A16 Input Address bus D0 to D7 Input output Data bus CE Input PROM enable input program pulse input OE Input Read strobe input to PROM PGM Input Program program inhibit input in PROM programming mode VDD Positive power sup...

Page 83: ...hey are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control mode In this mode these ports function as an external interrupt request input an external count clock input to the timer and crystal connection for subsystem clock oscillation a INTP0 to INTP6 INTP0 to INTP6 are external interrupt request input pins which can ...

Page 84: ...mit receive busy input and strobe output functions The following operating modes can be specified bit wise 1 Port mode These ports function as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 2 PM2 When they are used as input ports on chip pull up resistors can be used to them by defining the pull up resistor option register L PUOL 2 Control ...

Page 85: ...tion as 8 bit input output ports They can be specified bit wise as input or output ports with port mode register 3 PM3 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as timer input output clock output and buzzer output a TI1 and TI2 Pin for external count clock input to the 8 bit ti...

Page 86: ... output ports with port mode register 5 PM5 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode These ports function as high order address bus pins A8 to A15 in external memory expansion mode When pins are used as an address bus the on chip pull up resistor is automatically disabled 4 2 7 P60 to P67 Port 6 T...

Page 87: ...rts on chip pull up resistors can be used by defining the pull up resistor option register L PUOL 2 Control mode Port 7 functions as serial interface data input output and clock input output a SI2 SO2 Serial interface serial data input output pins b SCK2 Serial interface serial clock input output pin c RxD TxD Asynchronous serial interface serial data input output pins d ASCK Asynchronous serial i...

Page 88: ...e following operating modes can be specified bit wise 1 Port mode These ports function as 2 bit input output ports They can be specified bit wise as input or output ports with port mode register 13 PM13 When they are used as input ports on chip pull up resistors can be used by defining the pull up resistor option register H PUOH 2 Control mode These ports allow D A converter analog output ANO0 and...

Page 89: ...5 RESET This is a low level active system reset input pin 4 2 16 X1 and X2 Crystal resonator connect pins for main system clock oscillation For external clock supply input it to X1 and its inverted signal to X2 4 2 17 XT1 and XT2 Crystal resonator connect pins for subsystem clock oscillation For external clock supply input it to XT1 and its inverted signal to XT2 4 2 18 VDD Positive power supply p...

Page 90: ...heck the µPD78058FY Subseries at delivery Connect it directly to the VSS with the shortest possible wire in the normal operating mode When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin the user s program may not run normally Connect IC pins to VSS pins directly ...

Page 91: ...1 SO1 5 J P22 SCK1 8 D P23 STB 5 J P24 BUSY 8 D P25 SI0 SB0 SDA0 10 C P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 TO0 5 J Input output P31 TO1 P32 TO2 P33 TI1 8 D P34 TI2 P35 PCL 5 J P36 BUZ P37 P40 AD0 to P47 AD7 5 O Input output Connect independently via a resistor to VDD P50 A8 to P57 A15 5 J Input output Connect independently via a resistor to VDD or VSS 4 3 Input output Circuits and Recommended Connect...

Page 92: ...ct independently via a resistor to VDD or VSS P64 RD 5 D P65 WR P66 WAIT P67 ASTB P70 SI2 RxD 8 D P71 SO2 TxD 5 J P72 SCK2 ASCK 8 D P120 RTP0 to P127 RTP7 5 J P130 ANO0 to P131 ANO1 12 B Input output Connect independently via a resistor to VSS RESET 2 Input XT2 16 Leave open AVREF0 Connect to VSS AVREF1 Connect to VDD AVDD Connect to a separate power supply with the same potential as VDD AVSS Conn...

Page 93: ...ysteresis Characteristics Type 5 O Type 11 C Type 10 C Type 8 D pullup enable AVDD P ch IN OUT output disable data AVDD P ch N ch pullup enable AVDD P ch IN OUT output disable data AVDD P ch N ch pullup enable AVDD P ch IN OUT open drain output disable data AVDD P ch N ch pullup enable AVDD P ch IN OUT output disable data AVDD P ch N ch P ch comparator AVSS input enable VREF Threshold voltage AVSS...

Page 94: ...ut disable AVDD N ch IN OUT RD medium breakdown input buffer data P ch XT2 XT1 feedback cut off P ch Type 16 output disable AVDD AVDD N ch Mask Option IN OUT RD medium breakdown input buffer data P ch pullup enable AVDD P ch IN OUT output disable data AVDD P ch N ch input enable P ch N ch analog output voltage AVSS AVSS AVSS AVSS ...

Page 95: ... 32 8 bits Internal ROM 49152 8 bits BFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits External Memory 14976 8 bits Reserved Program memory space C000H BFFFH FA80H FA7FH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Function Regis...

Page 96: ...a memory space General Registers 32 8 bits Internal ROM 61440 8 bits EFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits Reserved Note Reserved Program memory space F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Speci...

Page 97: ...Data memory space General Registers 32 8 bits Internal PROM 61440 8 bits EFFFH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H CALLF Entry Area CALLT Table Area Vector Table Area Program Area Program Area Internal Buffer RAM 32 8 bits Reserved Program memory space F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Special Functio...

Page 98: ...tor table area The 64 byte area 0000H to 003FH is reserved as a vector table area The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area Of the 16 bit address low order 8 bits are stored at even addresses and high order 8 bits are stored at odd addresses Table 5 1 Vector Table Vector Table Address Interrupt Sources 0000H...

Page 99: ...buffer RAM is used to store transmit receive data of serial interface channel 1 in 3 wire serial I O mode with automatic transfer receive function If the 3 wire serial I O mode with automatic transfer receive function is not used the internal buffer RAM can also be used as normal RAM Internal buffer RAM can also be used as normal RAM 3 Internal expansion RAM µPD78058F 78058FY 78P058F 78P058FY only...

Page 100: ...eas FB00H to FFFFH where data memory is incorporated special addressing which matches the respective functions of the special function register SFR general purpose register etc is possible Figure 5 4 to 5 6 show the data memory addressing modes For details of each addressing refer to Section 5 4 Operand Address Addressing Figure 5 4 Data Memory Addressing µPD78056F 78056FY 0000H General Registers ...

Page 101: ...00H General Registers 32 8 bits Internal ROM 61440 8 bits Internal Buffer RAM 32 8 bits Reserved F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH F400H F3FFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits Internal Expansion RAM 1024 8 bits SFR Addressing Register Addressing Short Direct Addres...

Page 102: ... 0000H General Registers 32 8 bits Internal PROM 61440 8 bits Internal Buffer RAM 32 8 bits Reserved F000H EFFFH F800H F7FFH FAC0H FABFH FAE0H FADFH FEE0H FEDFH FF00H FEFFH FFFFH Internal High speed RAM 1024 8 bits Reserved FB00H FAFFH F400H F3FFH FF20H FF1FH FE20H FE1FH Special Function Registers SFRs 256 8 bits Internal Expansion RAM 1024 8 bits SFR Addressing Register Addressing Short Direct Ad...

Page 103: ...he instruction to be fetched When a branch instruction is executed immediate data and register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 5 7 Program Counter Format 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status ...

Page 104: ...banks In these flags the 2 bit information which indicates the register bank selected by SEL RBn instruction execution is stored d Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases e In service priority flag ISP This flag manages the priority of acknowledgeable maskable vectored interrupts When ISP 0 ackn...

Page 105: ... pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area FB00H to FEFFH can be set as the stack area Figure 5 9 Stack Pointer Format The SP is decremented ahead of write save to the stack memory and is incremented after read reset from the stack memory Each stack operation saves resets data as shown in Figures 5 10 and 5 11 Caut...

Page 106: ...n efficient program can be created by switching between a register for normal processing and a register for interruption for each bank Table 5 2 Corresponding Table of General Register Absolute Address Register Register Function Absolute Function Absolute Name Name Name Name BANK0 H R7 F E F F H BANK2 H R7 F E E F H L R6 F E E E H L R6 F E E E H D R5 F E E D H D R5 F E E D H E R4 F E F C H E R4 F ...

Page 107: ...ame BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEF7H FEE0H RP3 RP2 RP1 RP0 R7 15 0 7 0 R6 R5 R4 R3 R2 R1 R0 16 Bit Processing 8 Bit Processing FEE0H FEEFH FEE8H FEE7H BANK0 BANK1 BANK2 BANK3 FEFFH FEF8H FEF7H FEE0H HL DE BC AX H 15 0 7 0 L D E B C A X 16 Bit Processing 8 Bit Processing FEF0H FEEFH FEE8H FEE7H ...

Page 108: ...ulation can also be specified with an address 16 bit manipulation Describe the symbol reserved with assembler for the 16 bit manipulation instruction operand sfrp When addressing an address describe an even address Table 5 3 gives a list of special function registers The meaning of items in the table is as follows Symbol Symbols indicating the addresses of special function register These symbols a...

Page 109: ...t register 1 SIO1 FF1FH A D conversion result register ADCR R FF20H Port mode register 0 PM0 R W FFH FF21H Port mode register 1 PM1 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF25H Port mode register 5 PM5 FF26H Port mode register 6 PM6 FF27H Port mode register 7 PM7 FF2CH Port mode register 12 PM12 FF2DH Port mode register 13 PM13 FF30H Real time output buffer register L RTBL 0...

Page 110: ...egister SVA Undefined FF63H Interrupt timing specify register SINT 00H FF68H Serial operating mode register 1 CSIM1 FF69H Automatic data transmit receive control register ADTC FF6AH Automatic data transmit receive address pointer ADTP FF6BH Automatic data transmit receive interval specify register ADTI FF70H Asynchronous serial interface mode register ASIM FF71H Asynchronous serial interface statu...

Page 111: ...ng register IMS Note 2 FFF2H Oscillation mode selection register OSMS W 00H FFF3H Pull up resistor option register H PUOH R W FFF4H Internal expansion RAM size IXS W 0AH switching registerNote 3 FFF6H Key return mode register KRM R W 02H FFF7H Pull up resistor option register L PUOL 00H FFF8H Memory expansion mode register MM 10H FFF9H Watchdog timer mode register WDTM 00H FFFAH Oscillation stabil...

Page 112: ...nformation is set to the PC and branched by the following addressing For details of instructions refer to 78K 0 Series User s Manual Instruction U12326E 5 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displ...

Page 113: ...addr16 or CALLF addr11 instruction is executed The CALL addr16 and BR addr16 instruction can branch in the entire memory space The CALLF addr11 instruction branches to an area of addresses 0800H through 0FFFH Illustration In the case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 fa10 8 11 10 0 0 0 0 1 6 4 3 CALLF fa7 0 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr In the case of CALLF ...

Page 114: ...o the program counter PC and branched Before the CALLT addr5 instruction is executed table indirect addressing is performed This instruction references an address stored in the memory table at addresses 40H through 7FH and can branch in the entire memory space Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective Address 1 Effective Address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1...

Page 115: ...5 0 PC 8 7 5 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration ...

Page 116: ...gister to be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values which become decimal correction targets ROR4 ROL4 A register for storage of digit data which undergoes digit rotation Operand format Because implied addressing can be automatically ...

Page 117: ...g operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with function names X A C B E D L H AX BC DE and HL as well as absolute names R0 to R7 and RP0 to RP3 Description example MOV A C when selecting C register as r Ope...

Page 118: ...d by the immediate data in an instruction word Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration Memory 0 7 OP code saddr16 low saddr16 high ...

Page 119: ...0H through FF1FH to which short direct addressing is applied is a part of the entire SFR area To this area ports frequently accessed by the program and the compare registers and capture registers of timer event counters are mapped These SFRs can be manipulated with a short byte length and a few clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is a...

Page 120: ...dr offset α Description example MOV 0FE30H 50H when setting saddr to FE30H and immediate data to 50H Operation code 0 0 0 1 0 0 0 1 OP code 0 0 1 1 0 0 0 0 30H saddr offset 0 1 0 1 0 0 0 0 50H immediate data Illustration When 8 bit immediate data is 20H to FFH α 0 When 8 bit immediate data is 00H to 1FH α 1 ...

Page 121: ...rd This addressing is applied to the 240 byte spaces FF00H to FFCFH and FFE0H to FFFFH However the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 ...

Page 122: ...egister bank select flags RBS0 and RBS1 and register pair specify code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 16 0 8 D 7 E 0 7 7 0 A DE Memory Contents of addressed memory are transferred Memory address ...

Page 123: ...he HL register pair to be accessed is in the register bank specified by the register bank select flags RBS0 and RBS1 The offset data is first expanded as a positive number to 16 bits and then added A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H when setting byte to 10H ...

Page 124: ... a positive number and then added A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B Operation code 1 0 1 0 1 0 1 1 5 4 9 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatical...

Page 125: ...ration Every port is capable of 1 bit and 8 bit manipulations and can carry out considerably varied control operations Besides port functions the ports can also serve as on chip hardware input output pins Figure 6 1 Port Types Port 6 Port 0 Port 7 8 Port 1 Port 2 P00 P60 P67 P70 P72 P10 P07 P17 P20 P27 Port 13 Port 3 Port 4 P120 P127 P130 Port 12 P131 P30 P37 P40 to P47 Port 5 P50 P57 ...

Page 126: ...d as an input port an on chip pull up resistor can be used by software STB P24 BUSY P25 SI0 SB0 P26 SO0 SB1 P27 SCK0 P30 Port 3 TO0 P31 8 bit input output port TO1 P32 Input output mode can be specified bit wise TO2 P33 If used as an input port an on chip pull up resistor can be used by software TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 to P47 Port 4 AD0 to AD7 8 bit input output port Input output mode ...

Page 127: ...fied bit wise If used as an input port an on chip pull up resistor can be used by software Port 12 8 bit input output port Input output mode can be specified bit wise If used as an input port on chip pull up resistor can be used by software Port 13 2 bit input output port Input output mode can be specified bit wise If used as an input port on chip pull up resistor can be used by software Cautions ...

Page 128: ... can be specified bit wise SCK1 P23 If used as an input port an on chip pull up resistor can be used by software STB P24 BUSY P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 P27 SCK0 SCL P30 Port 3 TO0 P31 8 bit input output port TO1 P32 Input output mode can be specified bit wise TO2 P33 If used as an input port an on chip pull up resistor can be used by software TI1 P34 TI2 P35 PCL P36 BUZ P37 P40 to P47 Port...

Page 129: ...ified bit wise If used as an input port an on chip pull up resistor can be used by software Port 12 8 bit input output port Input output mode can be specified bit wise If used as an input port on chip pull up resistor can be used by software Port 13 2 bit input output port Input output mode can be specified bit wise If used as an input port on chip pull up resistor can be used by software Cautions...

Page 130: ...pins can specify the input mode output mode in 1 bit units with the port mode register 0 PM0 P00 and P07 pins are input only ports When P01 to P06 pins are used as input ports an on chip pull up resistor can be used to them in 6 bit units with a pull up resistor option register L PUOL Alternate functions include external interrupt request input external count clock input to the timer and crystal c...

Page 131: ...07 Block Diagram Figure 6 3 P01 to P06 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal P ch WRPM WRPORT RD WRPUO AVDD P01 INTP1 TI01 P02 INTP2 to P06 INTP6 Selector PUO0 Output Latch P01 to P06 PM01 to PM06 Internal bus ...

Page 132: ...tor option register L PUOL Alternate function includes an A D converter analog input RESET input sets port 1 to input mode Figure 6 4 shows a block diagram of port 1 Caution An on chip pull up resistor cannot be used for pins used as A D converter analog input Figure 6 4 P10 to P17 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 1 read signal WR Port 1 write signal...

Page 133: ...res 6 5 and 6 6 show block diagrams of port 2 Cautions 1 When used as a serial interface pin set the input output and output latch according to its functions For the setting method refer to Figure 16 4 Serial Operating Mode Register 0 Format and Figure 18 3 Serial Operating Mode Register 1 Format 2 When reading the pin state in SBI mode set PM2n bit of PM2 to 1 n 5 6 See 16 4 3 10 How to determine...

Page 134: ... P27 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal P ch WRPM WRPORT RD WRPUO AVDD Selector PUO2 Output Latch P22 P27 PM22 PM27 Internal bus Alternate Function P22 SCK1 P27 SCK0 ...

Page 135: ...nd strobe output RESET input sets port 2 to input mode Figures 6 7 and 6 8 show block diagrams of port 2 Caution When used as a serial interface pin set the input output and output latch according to its functions For the setting method refer to Figure 17 4 Serial Operating Mode Register 0 Format and Figure 18 3 Serial Operating Mode Register 1 Format Figure 6 7 P20 P21 P23 to P26 Block Diagram PU...

Page 136: ... Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal P ch WRPM WRPORT RD WRPUO AVDD Selector PUO2 Output Latch P22 and P27 PM22 PM27 Internal bus Alternate Function P22 SCK1 P27 SCK0 SCL ...

Page 137: ...th a pull up resistor option register L PUOL Alternate functions include timer input output clock output and buzzer output RESET input sets port 3 to input mode Figure 6 9 shows a block diagram of port 3 Figure 6 9 P30 to P37 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 3 read signal WR Port 3 write signal P ch WRPM WRPORT RD WRPUO AVDD Selector PUO3 Output Latc...

Page 138: ...ption register L PUOL The test input flag KRIF can be set to 1 by detecting falling edges Alternate functions include address data bus function in external memory expansion mode RESET input sets port 4 to input mode Figures 6 10 and 6 11 show a block diagram of port 4 and block diagram of falling edge detection circuit respectively Figure 6 10 P40 to P47 Block Diagram PUO Pull up resistor option r...

Page 139: ... units with a pull up resistor option register L PUOL Port 5 can drive LEDs directly Alternate function includes address bus function in external memory expansion mode RESET input sets port 5 to input mode Figure 6 12 shows a block diagram of port 5 Figure 6 12 P50 to P57 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 5 read signal WR Port 5 write signal P ch WRPM...

Page 140: ...of pull up resistor option register L PUOL Pins P60 to P63 can drive LEDs directly Pins P64 to P67 also serve as the control signal output in external memory expansion mode RESET input sets port 6 to input mode Figures 6 13 and 6 14 show block diagrams of port 6 Cautions 1 When external wait is not used in external memory expansion mode P66 can be used as an input output port 2 The value of the lo...

Page 141: ...stor option register PM Port mode register RD Port 6 read signal WR Port 6 write signal WRPM WRPORT RD AVDD Selector Output Latch P60 to P63 PM60 to PM63 Internal bus P60 to P63 Mask Option Resistor Mask ROM products only PROM versions have no pull up resistor P ch WRPM WRPORT RD WRPUO AVDD Selector PUO6 Output Latch P64 to P67 PM64 to PM67 Internal bus P64 RD P65 WR P66 WAIT P67 ASTB ...

Page 142: ...erface channel 2 data input output and clock input output RESET input sets the input mode Figures 6 15 and 6 16 show block diagrams of port 7 Caution When used as a serial interface pin set the input output and output latch according to its functions For the setting method refer to Table 19 2 Serial Interface Channel 2 Operating Mode Settings of List Figure 6 15 P70 Block Diagram PUO Pull up resis...

Page 143: ...Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 7 read signal WR Port 7 write signal P ch WRPM WRPORT RD WRPUO AVDD Selector PUO7 Output Latch P71 and P72 PM71 PM72 Internal bus Alternate Function P71 SO2 TxD P72 SCK2 ASCK ...

Page 144: ...an be used as an 8 bit unit by means of pull up resistor option register H PUOH Alternate function includes real time output RESET input sets the input mode Figure 6 17 shows a block diagram of port 12 Figure 6 17 P120 to P127 Block Diagram PUO Pull up resistor option register PM Port mode register RD Port 12 read signal WR Port 12 write signal P ch WRPM WRPORT RD WRPUO AVDD Selector PUO12 Output ...

Page 145: ...lock diagram of port 13 Caution When only either one of the D A converter channels is used with AVREF1 VDD the other pins that are not used as analog outputs must be set as follows Set PM13 bit of the port mode register 13 PM13 to 1 input mode and connect the pin to VSS Set PM13 bit of the port mode register 13 PM13 to 0 output mode and the output latch to 0 to output low level from the pin Figure...

Page 146: ...e independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets registers to FFH When port pins are used as the dual function pins set the port mode register and output latch according to Table 6 5 Cautions 1 Pins P00 and P07 are input only pins 2 As port 0 has a dual function as external interrupt request input when the port function output mode is specified and the out...

Page 147: ... Name P PM Input Output Pin Name Notes 1 If these ports are read out when these pins are used in the alternate function mode undefined values are read 2 When the P40 to P47 pins P50 to P57 pins and P64 to P67 pins are used for alternate functions set the function by the memory expansion mode register MM Cautions 1 When not using external wait in the external memory extension mode the P66 pin can b...

Page 148: ...27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 PM6 PM7 FF26H FF27H FFH FFH R W R W PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 1 1 1 1 1 PM72 PM71 PM70 PM05 PM04 PM12 PM13 PMmn Pmn Pin Input Output Mode Selection m 0 to 3 5 to 7 12 13 n 0 to 7 0 1 Output mode output buffer ON Input mode output buffer OFF FF2CH FF2DH FFH FFH R W R W...

Page 149: ...nput sets this register to 00H Cautions 1 P00 and P07 pins do not incorporate a pull up resistor 2 When ports 1 4 5 and P64 to P67 pins are used as dual function pins an on chip pull up resistor cannot be used even if 1 is set in PUOm bit of PUOH PUOL m 1 4 to 6 3 Pins P60 to P63 can be connected with pull up resistor by mask option only for mask ROM version Figure 6 20 Pull Up Resistor Option Reg...

Page 150: ...rt 4 input output MM also sets the wait count and external expansion area 0 0 PW1 0 MM FFF8H 10H R W 7 6 5 4 3 2 Symbol Address After Reset R W 1 PW0 MM2 MM1 MM0 0 MM2 MM1 MM0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1 1 1 1 Other than above Setting prohibited Single chip Memory Expansion Mode Selection Single chip mode 256 byte mode 4 Kbyte mode 16 Kbyte mode Full address modeNote Memory expansion mode AD0 to...

Page 151: ...Standby mode release disabled Address After Reset R W 02H R W 4 Key return mode register KRM This register sets enabling disabling of standby function release by a key return signal falling edge detection of port 4 KRM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets KRM to 02H Figure 6 22 Key Return Mode Register Format Caution When falling edge detection of port4 is ...

Page 152: ... the output buffer is OFF the pin status does not change Once data is written to the output latch it is retained until data is written to the output latch again Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specifie...

Page 153: ... change Caution In the case of 1 bit memory manipulation instruction although a single bit is manipulated the port is accessed as an 8 bit unit Therefore on a port with a mixture of input and output pins the output latch contents for pins specified as input are undefined even for bits other than the manipulated bit 6 5 Selection of Mask Option The following mask option is provided in mask ROM vers...

Page 154: ...154 MEMO ...

Page 155: ...ubsystem clock oscillator The circuit oscillates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used not using the internal feedback resistor can be set by the processor clock control register PCC This enables to decrease power consumption in the STOP mode 7 2 Clock Generator Configuration The clock generator consists of the following hardware T...

Page 156: ...C FRC CLS CSS PCC2 PCC1 Internal Bus Standby Control Circuit To INTP0 Sampling Clock 2 fXX 22 fXX 23 fXX 24 fXX Prescaler Clock to Peripheral Hardware Prescaler Oscillation Mode Selection Register Watch Timer Clock Output Function fXX CPU Clock fCPU Wait Control Circuit Scaler Selector fX fXT 2 fX MCS Processor Clock Control Register 2 fXT PCC0 3 Selector 1 2 ...

Page 157: ...ster OSMS 1 Processor clock control register PCC The PCC sets whether to use CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem clock oscillator internal feedback resistor The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 04H Figure 7 2 Subsystem Clock Feedback Resistor FRC P ch Feedback resistor XT1 XT...

Page 158: ...ction register OSMS MCC FRC CLS CSS PCC2 PCC1 PCC0 PCC CLS 0 1 Main system clock Subsystem clock FFFBH 04H R WNote 1 7 6 5 4 Symbol Address After Reset R W 0 7 6 3 2 0 1 CSS 0 0 fXX 2 PCC2 CPU CIock Selection fCPU PCC1 PCC0 CPU Clock Status 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 fXX 22 fXX 23 fXX 2 4 fXT 2 fXX Setting prohibited Other than above FRC 0 1 Internal feedback resistor ...

Page 159: ... with 8 bit memory manipulation instruction RESET input sets OSMS to 00H Figure 7 4 Oscillation Mode Selection Register Format Caution 1 Writing to OSMS should be performed only immediately after reset signal release and before peripheral hardware operation starts As shown in Figure 7 5 below writing data including same data as previous to OSMS cause delay of main system clock cycle up to 2 fx dur...

Page 160: ...ing to OSMS Caution 2 When writing 1 to MCS VDD must be 2 7 V or higher before the write execution Remarks fxx Main system clock frequency fx or fx 2 fx Main system clock oscillation frequency Write to OSMS MCS 0 fXX Max 2 fX Operating at fXX fX 2 MCS 0 Operating at fXX fX 2 MCS 0 ...

Page 161: ...se clock signal to the X2 pin Figure 7 6 shows an external circuit of the main system clock oscillator Figure 7 6 External Circuit of Main System Clock Oscillator a Crystal and ceramic oscillation b External clock Caution When an external clock is input do not execute the STOP instruction or set MCC bit 7 of the processor clock control register PCC to 1 If the STOP instruction is executed or MCC i...

Page 162: ...event any effects from wiring capacities Minimize the wiring length Do not allow wiring to intersect with other signal lines Do not allow wiring to come near changing high current Set the potential of the grounding position of the oscillator capacitor to that of VSS Do not ground to any ground pattern where high current is present Do not fetch signals from the oscillator Take special note of the f...

Page 163: ...n using a subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Cautions 2 If XT2 and X1 are wired in parallel the crosstalk noise of X1 may be transmitted along XT2 and cause malfunctions To prevent that from occurring it is recommended to wire XT2 and X1 so that they are not in parallel and to correct the IC pin between XT2 and X1 directl...

Page 164: ...ons and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to VDD XT2 Leave open In this state however some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops To suppress the leakage current disconnect the above internal feedback resistor by using the bit 6 FRC of the processor clock control register PCC In this ...

Page 165: ...le In a system where the subsystem clock is not used the current consumption in the STOP mode can be further reduced by specifying with bit 6 FRC of the PCC not to use the feedback resistor d The PCC can be used to select the subsystem clock and to operate the system with low current consumption 122 µs when operated at 32 768 kHz e With the subsystem clock selected main system clock oscillation ca...

Page 166: ... instruction execution time can be changed by bits 0 to 2 PCC0 to PCC2 of the PCC b If bit 7 MCC of the PCC is set to 1 when operated with the main system clock the main system clock oscillation does not stop When bit 4 CSS of the PCC is set to 1 and the operation is switched to subsystem clock operation CLS 1 after that the main system clock oscillation stops see Figure 7 9 Figure 7 9 Main System...

Page 167: ... bits 0 to 2 PCC0 to PCC2 of the PCC b Watchdog timer counting stops Caution Do not execute the STOP instruction while the subsystem clock is in operation 7 6 Changing System Clock and CPU Clock Settings 7 6 1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits 0 to 2 PCC0 to PCC2 and bit 4 CSS of the processor clock ...

Page 168: ... fX 64fXT instruction 3 instructions MSC 1 MSC 0 Set Values After Switchover Set Values before Switchover CSS CSS CSS CSS CSS 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction 1 instruction CSS 1 instruction 1 instruction Remarks 1 One instruction is the minimum instruction execution time with the pre switchover CPU clock 2 MCS Oscillation mode selection register ...

Page 169: ...clock 12 8 µs when operated at 5 0 MHz 2 After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speeds the processor clock control register PCC and oscillation mode selection register OSMS are rewritten and the maximum speed operation is carried out 3 Upon detection of a decrease of the VDD voltage due to an interrupt request signal the main system cloc...

Page 170: ...170 MEMO ...

Page 171: ...tput square waves with any selected frequency Two 8 bit timer event counters can be used as one 16 bit timer event counter See CHAPTER 9 8 BIT TIMER EVENT COUNTER 3 Watch timer TM3 This timer can set a flag every 0 5 sec and simultaneously generates interrupts request at the preset time intervals See CHAPTER 10 WATCH TIMER 4 Watchdog timer WDTM WDTM can perform the watchdog timer function or gener...

Page 172: ...tput One shot pulse output Interrupt request Test input Notes 1 Watch timer can perform both watch timer and interval timer functions at the same time 2 Watchdog timer can perform either the watchdog timer function or the interval timer function 3 When capture compare registers 00 01 CR00 CR01 are specified as compare registers Function Operation mode Watch Timer Watchdog Timer 16 bit Timer 8 bit ...

Page 173: ...le 2 1 fX 216 1 fX 1 fX 400 ns 13 1 ms 200 ns 2 1 fX 22 1 fX 216 1 fX 217 1 fX 1 fX 2 1 fX 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 1 fX 23 1 fX 217 1 fX 218 1 fX 2 1 fX 22 1 fX 800 ns 1 6 µs 26 2 ms 52 4 ms 400 ns 800 ns 23 1 fX 24 1 fX 218 1 fX 219 1 fX 22 1 fX 23 1 fX 1 6 µs 3 2 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 2 watch timer output cycle 216 watch timer output cycle Watch timer output ed...

Page 174: ...er output edge cycle Remarks 1 fX Main system clock oscillation frequency 2 MCS Bit 0 of oscillation mode selection register OSMS 3 Values in parentheses when operated at fX 5 0 MHz 6 One shot pulse output TM0 is able to output one shot pulse which can set any width of output pulse 8 3 16 Bit Timer Event Counter Configuration The 16 bit timer event counter consists of the following hardware Table ...

Page 175: ... Circuit TMC03 TMC02 TMC01 OVF0 OSPTOSPETOC04 LVS0 LVR0TOC01TOE0 16 Bit Timer Mode Control Register 16 Bit Timer Output Control Register 2 PWM Pulse Output Controller 16 Bit Timer Event Counter Output Control Circuit Note 2 TMC01 to TMC03 INTP0 INTTM01 TO0 P30 INTP1 INTTM00 Match TMC01 to TMC03 3 16 Bit Timer Register TM0 TI00 P00 INTP0 Note 1 CRC02 Figure 8 1 16 Bit Timer Event Counter Block Diag...

Page 176: ...tput Control Circuit Edge Detection Circuit TI00 P00 INTP0 OSPT 16 Bit Timer Output Control Register OSPE TOC04 LVS0 LVR0 TOC01 TOE0 Selector Selector INV S R Q 3 Level Inversion CRC02 INTTM01 CRC00 INTTM00 One Shot Pulse Output Control Circuit 2 ES11 ES10 External Interrupt Mode Register 0 16 Bit Timer Mode Control Register TMC03 TMC02 TMC01 P30 Output Latch PM30 Port Mode Register 3 TO0 P30 Inte...

Page 177: ...Setting prohibited 1 1 Both rising and falling edges No capture operation Remark ES10 ES11 Bits 2 and 3 of external interrupt mode register 0 INTM0 CR00 is set by a 16 bit memory manipulation instruction After RESET input the value of CR00 is undefined Cautions 1 Set the data of PWM 14 bits to the higher 14 bits of CR00 At this time clear the lower 2 bits to 00 2 Set a value other than 0000H to CR...

Page 178: ...set value of CR01 is lost 8 4 16 Bit Timer Event Counter Control Registers The following seven types of registers are used to control the 16 bit timer event counter Timer clock select register 0 TCL0 16 bit timer mode control register TMC0 Capture compare control register 0 CRC0 16 bit timer output control register TOC0 Port mode register 3 PM3 External interrupt mode register 0 INTM0 Sampling clo...

Page 179: ...prohibited fX 5 0 MHz 0 1 0 fXX fX 5 0 MHz fX 2 2 5 MHz 0 1 1 fXX 2 fX 2 2 5 MHz fX 2 2 1 25 MHz 1 0 0 fXX 2 2 fX 2 2 1 25 MHz fX 2 3 625 kHz 1 1 1 Watch timer output INTTM 3 MCS 1 16 Bit Timer Register Count Clock Selection MCS 0 Other than above Setting prohibited CLOE 1 Output enabled PCL Output Control 0 Output disabled Figure 8 3 Timer Clock Selection Register 0 Format Cautions 1 The valid ed...

Page 180: ...theses apply to operation with fX 5 0 MHz of fXT 32 768 kHz 2 16 bit timer mode control register TMC0 This register sets the 16 bit timer operating mode the 16 bit timer register clear mode and output timing and detects an overflow TMC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC0 value to 00H Caution The 16 bit timer register starts operation at the moment a ...

Page 181: ...TM0 and CR01 Match between TM0 and CR00 match between TM0 and CR01 or TI00 valid edge Clear start on TI00 valid edge Clear start on match between TM0 and CR00 Generated on match between TM0 and CR00 and match between TM0 and CR01 Figure 8 4 16 Bit Timer Mode Control Register Format Cautions 1 Switch the clear mode and the T00 output timing after stopping the timer operation by setting TMC01 to TMC...

Page 182: ...s CRC0 value to 04H Figure 8 5 Capture Compare Control Register 0 Format Cautions 1 The timer operation must be stopped before setting CRC0 2 When clear start mode on a match between TM0 and CR00 is selected with the 16 bit timer mode control register TMC0 CR00 should not be specified as a capture register 4 16 bit timer output control register TOC0 This register controls the operation of the 16 b...

Page 183: ...g 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited TOC04 Timer output F F control by match of CR01 and TM0 0 Inversion operation disabled 1 Inversion operation enabled OSPE One Shot Pulse Output Control 0 Continuous pulse output 1 One shot pulse output OSPT Control of One Shot Pulse Output Trigger by Software 0 One shot pulse trigger not used 1 One shot ...

Page 184: ...election n 0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF 5 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P30 TO0 pin for timer output set PM30 and output latch of P30 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 value to FFH Figure 8 7 Port Mode Register 3 Format ...

Page 185: ...rising edges 1 ES31 INTP2 Valid Edge Selection ES30 0 Falling edge 0 0 Rising edge 1 1 Setting prohibited 0 1 Both falling and rising edges 1 6 External interrupt mode register 0 INTM0 This register is used to set INTP0 to INTP2 valid edges INTM0 is set with an 8 bit memory manipulation instruction RESET input sets INTM0 value to 00H Figure 8 8 External Interrupt Mode Register 0 Format Caution Bef...

Page 186: ...eception is carried out using INTP0 digital noise is removed with sampling clock SCS is set with an 8 bit memory manipulation instruction RESET input sets SCS value to 00H Figure 8 9 Sampling Clock Select Register Format Caution fXX 2N is the clock supplied to the CPU and fXX 25 fXX 26 and fXX 27 are clocks supplied to peripheral hardware fXX 2N is stopped in HALT mode Remarks 1 N Value set in bit...

Page 187: ...imer register TM0 matches the value set to CR00 counting continues with the TM0 value cleared to 0 and the interrupt request signal INTTM00 is generated Count clock of the 16 bit timer event counter can be selected with bits 4 to 6 TCL04 to TCL06 of the timer clock select register 0 TCL0 For the operation when the value of the compare register has been changed during timer count operation refer to...

Page 188: ...r Circuit INTTM00 Figure 8 11 Interval Timer Configuration Diagram Figure 8 12 Interval Timer Operation Timings Remark Interval time N 1 t N 0001H to FFFFH t Count Clock TM0 Count Value CR00 INTTM00 TO0 Interval Time Interval Time Interval Time 0000 0001 N 0000 0001 N 0000 0001 N Count Start Clear Clear N N N N Interrupt Request Acknowledge Interrupt Request Acknowledge ...

Page 189: ...utput operations Setting the 16 bit timer mode control register TMC0 capture compare control register 0 CRC0 and the 16 bit timer output control register TOC0 as shown in Figure 8 13 allows operation as PWM output Pulses with the duty rate determined by the value set in 16 bit capture compare register 00 CR00 beforehand are output from the TO0 P30 pin Set the active level width of the PWM pulse to...

Page 190: ... 1 0 0 0 0 0 0 OVF0 TMC01 TMC02 TMC03 PWM mode Figure 8 13 Control Register Settings for PWM Output Operation a 16 bit timer mode control register TMC0 b Capture compare control register 0 CRC0 c 16 bit timer output control register TOC0 Remarks 1 0 1 Setting 0 or 1 allows another function to be used simultaneously with PWM output See the description of the respective control registers for details...

Page 191: ...l switching circuit reference voltage Figure 8 14 Example of D A Converter Configuration with PWM Output capture compare register 00 CR00 value Figure 8 15 shows an example in which PWM output is converted to an analog voltage and used in a voltage synthesizer type TV tuner Figure 8 15 TV Tuner Application Circuit Example Switching Circuit TO0 P30 PWM signal VREF Low Pass Filter Analog Output VAN ...

Page 192: ...ode control register TMC0 and capture compare control register 0 CRC0 as shown in Figure 8 16 allows operation as PPG Programmable Pulse Generator output In the PPG output operation square waves are output from the TO0 P30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16 bit capture compare register 01 CR01 and in 16 bit capture compare register 00 CR...

Page 193: ...specified by external interrupt mode register 0 INTM0 is input to the TI00 P00 pin the value of TM0 is taken into 16 bit capture compare register 01 CR01 and an external interrupt request signal INTP0 is set Any of three valid edge specifications can be selected rising falling or both edges by means of bits 2 and 3 ES10 and ES11 of INTM0 For valid edge detection sampling is performed at the interv...

Page 194: ...00 INTP00 Count Clock TM0 Count Value TI00 Pin Input CR01 Captured Value INTP0 OVF0 0000 0001 D0 D1 FFFF 0000 D2 D3 D0 D1 D2 D3 D1 D0 t 10000H D1 D2 t D3 D2 t t Figure 8 18 Configuration Diagram for Pulse Width Measurement by Free Running Counter Figure 8 19 Timing of Pulse Width Measurement Operation by Free Running Counter and One Capture Register with Both Edges Specified ...

Page 195: ...nd 5 ES20 and ES21 of INTM0 is input to the TI01 P01 pin the value of TM0 is taken into 16 bit capture compare register 00 CR00 and an external interrupt request signal INTP1 is set Any of three edge specifications can be selected rising falling or both edges as the valid edge for the TI00 P00 pin and the TI01 P01 pin by means of bits 2 and 3 ES01 and ES11 and bits 4 and 5 ES20 and ES21 of INTM0 r...

Page 196: ...nput CR01 Captured Value INTP0 TI01 Pin Input t CR00 Captured Value INTP1 OVF0 D1 D0 t 10000H D1 D2 t 10000H D1 D2 1 t D3 D2 t 0000 0001 D0 D1 0000 D3 D2 FFFF D0 D1 D3 D2 D1 Figure 8 21 Timing of Pulse Width Measurement Operation with Free Running Counter with Both Edges Specified ...

Page 197: ...into CR01 the value of TM0 is taken into 16 bit capture compare register 00 CR00 Either of two edge specifications can be selected rising or falling as the valid edges for the TI00 P00 pin by means of bits 2 and 3 ES10 and ES11 of INTM0 For TI00 P00 pin valid edge detection sampling is performed at the interval selected by means of the sampling clock selection register SCS and a capture operation ...

Page 198: ...00 Pin Input CR01 Captured Value CR00 Captured Value INTP0 OVF0 D1 D0 t 10000H D1 D2 t D3 D2 t D1 D3 D0 D2 D3 D2 0000 FFFF D1 D0 0000 0001 t Figure 8 23 Timing of Pulse Width Measurement Operation by Free Running Counter and Two Capture Registers with Rising Edge Specified ...

Page 199: ...lid edge detection the sampling is performed by a cycle selected by the sampling clock selection register SCS and a capture operation is only performed when a valid level is detected twice thus eliminating noise with a short pulse width Caution If the valid edge of TI00 P00 is specified to be both rising and falling edge the 16 bit capture compare register 00 CR00 cannot perform the capture operat...

Page 200: ...cleared to 0 and the interrupt request signal INTTM00 is generated Set a value for CR00 other than 0000H 1 pulse count operation is not possible The rising edge the falling edge or both edges can be selected with bits 2 and 3 ES10 and ES11 of INTM0 Because operation is carried out only after the valid edge is detected twice by sampling at the interval selected with the sampling clock select regist...

Page 201: ...ompare Register 00 CR00 Clear INTTM00 INTP0 16 Bit Timer Register TM0 16 Bit Capture Compare Register 01 CR01 Internal Bus TI00 Valid Edge OVF0 Figure 8 27 External Event Counter Configuration Diagram Figure 8 28 External Event Counter Operation Timings with Rising Edge Specified Caution When reading the external event counter count value TM0 should be read ...

Page 202: ...ed frequency with the count value set previously in the 16 bit capture conveyor register 00 CR00 as the interval The TO0 P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 TOE0 and bit 1 TOC01 of the 16 bit timer output control register TOC0 to 1 This enables a square wave with any selected frequency to be output Figure 8 29 Control Register Settings ...

Page 203: ...00 input edge cycle 2 1 fX 216 1 fX 1 fX 400 ns 13 1 ms 200 ns 2 1 fX 22 1 fX 216 1 fX 217 1 fX 1 fX 2 1 fX 400 ns 800 ns 13 1 ms 26 2 ms 200 ns 400 ns 22 1 fX 23 1 fX 217 1 fX 218 1 fX 2 1 fX 22 1 fX 800 ns 1 6 µs 26 2 ms 52 4 ms 400 ns 800 ns 23 1 fX 24 1 fX 218 1 fX 219 1 fX 22 1 fX 23 1 fX 1 6 µs 3 2 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 2 watch timer output cycle 216 watch timer output cycle Watc...

Page 204: ...C0 by software a one shot pulse is output from the TO0 P30 pin By setting 1 in OSPT the 16 bit timer event counter is cleared and started and output is activated by the count value set beforehand in 16 bit capture compare register 01 CR01 Thereafter output is inactivated by the count value set beforehand in 16 bit capture compare register 00 CR00 TM0 continues to operate after one shot pulse is ou...

Page 205: ... Output 0000 0001 N N 1 0000 N 1 N M 1 M 0000 0001 0002 N M N M N M N M Set 0CH to TMC0 TM0 count start Figure 8 32 Timing of One Shot Pulse Output Operation Using Software Trigger Caution The 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set to TMC01 to TMC03 respectively ...

Page 206: ...ng falling or both edges as the valid edges for the TI00 P00 pin by means of bits 2 and 3 ES10 and ES11 of external interrupt mode register 0 INTM0 When a valid edge is input to the TI00 P00 pin the 16 bit timer event counter is cleared and started and output is activated by the count values set beforehand in 16 bit capture compare register 01 CR01 Thereafter output is inactivated by the count val...

Page 207: ...0000 0001 0000 N N 1 N 2 M 2 M 1 M M 1 M 2 M 3 N M N M N M N M Set 08H to TMC0 TM0 count start Figure 8 34 Timing of One Shot Pulse Output Operation Using External Trigger with Rising Edge Specified Caution The 16 bit timer register starts operation at the moment a value other than 0 0 0 operation stop mode is set to TMC01 to TMC03 respectively ...

Page 208: ...ng 2 16 bit compare register setting Set a value other than 0000H to the 16 bit capture compare register 00 CR00 Thus when using the 16 bit capture compare register as event counter one pulse count operation cannot be carried out 3 Operation after compare register change during timer count operation If the value after the 16 bit capture compare register CR00 is changed is smaller than that of the ...

Page 209: ...alid edge setting Set the valid edge of the TI00 P00 INTP0 pin after setting bits 1 to 3 TMC01 to TMC03 of the 16 bit timer mode control register TMC0 to 0 0 0 respectively and then stopping timer operation Valid edge setting is carried out with bits 2 and 3 ES10 and ES11 of external interrupt mode register 0 INTM0 6 Re trigger of one shot pulse a One shot pulse output using software When outputti...

Page 210: ...TM00 FFFFH FFFEH FFFFH 0000H 0001H 7 Operation of OVF0 flag OFV0 flag is set to 1 in the following case The clear start mode on match between TM0 and CR00 is selected CR00 is set to FFFFH When TM0 is counted up from FFFFH to 0000H Figure 8 38 Operation Timing of OVF0 Flag ...

Page 211: ... timer event counter channels are separately used 8 bit timer event counter mode and a mode in which the two 8 bit timer event counter channels are used combined as a 16 bit timer event counter 16 bit timer event counter mode 9 1 1 8 bit timer event counter mode The 8 bit timer event counters 1 and 2 TM1 and TM2 have the following functions Interval timer External event counter Square wave output ...

Page 212: ...2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 1 fX 217 1 fX 28 1 fX 29 1 fX 51 2 µs 102 4 µ...

Page 213: ... 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 ...

Page 214: ...1 fX 25 1 fX 220 1 fX 221 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 221 1 fX 222 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 222 1 fX 223 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 1 fX 28 1 fX 223 1 fX 224 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 1 7 s 3 4 s 25 6 µs 51 2 µs 28 1 fX 29 1 fX 22...

Page 215: ...9 7 ms 1 6 µs 3 2 µs 24 1 fX 25 1 fX 220 1 fX 221 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 221 1 fX 222 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 222 1 fX 223 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 1 fX 28 1 fX 223 1 fX 224 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 1 7 s 3 4 s 25 6 µs 51...

Page 216: ... 8 Bit Timer Event Counter Configuration Item Configuration Timer register 8 bits 2 TM1 TM2 Register Compare register 8 bits 2 CR10 CR20 Timer output 2 TO1 TO2 Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 Note Control register Note See Figure 6 9 P30 to P37 Block Diagram ...

Page 217: ...2 9 fXX 2 11 TI1 P33 fXX 2 fXX 2 9 fXX 2 11 TI2 P34 4 TCL 17 TCL 16 TCL 15 TCL 14 TCL 13 TCL 12 TCL 11 TCL 10 Timer Clock Select Register 1 8 Bit Timer Mode Control Register TMC12 TCE2 TCE1 Internal Bus LVS2 LVR2 TOC 15 TOE2LVS1 LVR1 TOC 11 TOE1 4 8 Bit Timer Register 2 TM2 8 Bit Timer Event Counter Output Control Circuit 1 8 Bit Timer Output Control Register 8 Bit Timer Event Counter Output Contr...

Page 218: ...utput Latch TOE1 PM31 TO1 P31 Level F F LV1 Figure 9 2 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 1 Remark The section in the broken line is an output control circuit Figure 9 3 Block Diagram of 8 Bit Timer Event Counter Output Control Circuit 2 Remarks 1 The section in the broken line is an output control circuit 2 fSCK Serial clock frequency ...

Page 219: ...t makes CR10 and CR20 undefined Cautions 1 When using the compare register as a 16 bit timer event counter be sure to stop the timer operation before setting data 2 If the values after CR10 and CR20 are changed smaller than those of the 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the values after CR10 and CR20 change are smaller...

Page 220: ...bit timer event counter Timer clock select register 1 TCL1 8 bit timer mode control register 1 TMC1 8 bit timer output control register TOC1 Port mode register 3 PM3 1 Timer clock select register 1 TCL1 This register sets count clocks of 8 bit timer registers 1 and 2 TCL1 is set with an 8 bit memory manipulation instruction RESET input sets TCL1 to 00H ...

Page 221: ...0 TI2 falling edge 0 0 0 1 TI2 rising edge 0 1 1 0 0 1 1 1 fXX 2 fX 2 2 5 MHz fX 2 2 1 25 MHz 1 0 0 0 fXX 2 2 fX 2 2 1 25 MHz fX 2 3 625 kHz 1 0 0 1 fXX 2 3 fX 2 3 625 kHz fX 2 4 313 kHz 1 0 1 0 fXX 2 4 fX 2 4 313 kHz fX 2 5 156 kHz 1 0 1 1 fXX 2 5 fX 2 5 156 kHz fX 2 6 78 1 kHz 1 1 0 0 fXX 2 6 fX 2 6 78 1 kHz fX 2 7 39 1 kHz 1 1 0 1 fXX 2 7 fX 2 7 39 1 kHz fX 2 8 19 5 kHz 1 1 1 0 fXX 2 8 fX 2 8 1...

Page 222: ...r 2 channel mode TM1 TM2 16 Bit timer register 1 channel mode TMS 0 1 2 8 bit timer mode control register TMC1 This register enables stops operation of 8 bit timer registers 1 and 2 and sets the operating mode of 8 bit timer register 1 and 2 TMC1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC1 to 00H Figure 9 5 8 Bit Timer Mode Control Register Format Cautions 1 ...

Page 223: ...Bit Timer Event Counter 2 Timer Output F F Control 0 Inverted operation disable 1 Inverted operation enable LVS2 LVR2 8 Bit Timer Event Counter 2 Timer Output F F Status Set 0 0 Unchanged 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited 3 8 bit timer output control register TOC1 This register controls operation of 8 bit timer event counter output control circuits 1 an...

Page 224: ...0 to 7 0 Output mode output buffer ON 1 Input mode output buffer OFF 4 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P31 TO1 and P32 TO2 pins for timer output set PM31 PM32 and output latches of P31 and P32 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 9 7 Port Mode Register 3 Format ...

Page 225: ...INTTM1 and INTTM2 are generated Count clock of TM1 can be selected with bits 0 to 3 TCL10 to TCL13 of the timer clock select register 1 TCL1 Count clock of TM2 can be selected with bits 4 to 7 TCL14 to TCL17 of the timer clock select register 1 TCL1 For the operation when the value of the compare register has been changed during timer count operation refer to section 9 5 3 Operation after compare ...

Page 226: ...X 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 1 fX 217 1 fX 28 1 fX 29 1 fX 51 2 µs 102 4 µs 13 1 ms 26 2 ms 51 2 µs 102 4 µs 29 1 fX 210 1 fX 217 1 fX 218 1 fX 29 1 fX 210 1...

Page 227: ...X 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ms 6 55 ms 12 8 µs 25 6 µs 27 1 fX 28 1 fX 215 1 fX 216 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 6 55 ms 13 1 ms 25 6 µs 51 2 µs 28 1 fX 29 1 fX 216 1 fX 217 1 fX 28 1 fX 29 1 fX 51 2 µs 102 4 µs 13 1 ms 26 2 ms 51 2 µs 102 4 µs 29 1 fX 210 1 fX 217 1 fX 218 1 fX 29 1 fX 210 1...

Page 228: ...mer registers 1 and 2 TM1 and TM2 TM1 and TM2 are incremented each time the valid edge specified with the timer clock select register TCL1 is input Either the rising or falling edge can be selected When the TM1 and TM2 counted values match the values of 8 bit compare registers CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signals INTTM1 and INTTM2 are generated Figure 9 9 Ex...

Page 229: ...ns 1 6 µs 204 8 µs 409 6 µs 800 ns 1 6 µs 23 1 fX 24 1 fX 211 1 fX 212 1 fX 23 1 fX 24 1 fX 1 6 µs 3 2 µs 409 6 µs 819 2 µs 1 6 µs 3 2 µs 24 1 fX 25 1 fX 212 1 fX 213 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 819 2 µs 1 64 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 213 1 fX 214 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 1 64 ms 3 28 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 214 1 fX 215 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 3 28 ...

Page 230: ...operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset in the 2 channel 8 bit compare registers CR10 and CR20 To set the count value assign the higher 8 bits of the value to CR20 and the lower 8 bits of the value to CR10 For the count values interval times that can be set refer to Table 9 9 When the count value of the 8 bit timer register 1 T...

Page 231: ...ounter output control circuit 1 is inverted Thus when using 8 bit timer event counter as 16 bit interval timer set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1 acknowledgment When reading the 16 bit timer register TMS count value use the 16 bit memory manipu lation instruction Count Clock TMS TM1 TM2 Count Value CR10 CR20 INTTM2 TO2 Interval Time Interval Time Interval Time Interrupt Request ...

Page 232: ...5 1 fX 26 1 fX 221 1 fX 222 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 419 4 ms 838 9 ms 6 4 µs 12 8 µs 26 1 fX 27 1 fX 222 1 fX 223 1 fX 26 1 fX 27 1 fX 12 8 µs 25 6 µs 838 9 ms 1 7 s 12 8 µs 25 6 µs 27 1 fX 28 1 fX 223 1 fX 224 1 fX 27 1 fX 28 1 fX 25 6 µs 51 2 µs 1 7 s 3 4 s 25 6 µs 51 2 µs 28 1 fX 29 1 fX 224 1 fX 225 1 fX 28 1 fX 29 1 fX 51 2 µs 102 4 µs 3 4 s 6 7 s 51 2 µs 102 4 µs 29 1 fX 210 1 fX...

Page 233: ...e values of 8 bit compare registers 10 and 20 CR10 and CR20 TM1 and TM2 are cleared to 0 and the interrupt request signal INTTM2 is generated Figure 9 12 External Event Counter Operation Timings with Rising Edge Specified Caution Even if the 16 bit timer event counter mode is used when the TM1 count value matches the CR10 value interrupt request INTTM1 is generated and the F F of 8 bit timer event...

Page 234: ...00 ns 26 2 ms 52 4 ms 400 ns 800 ns 22 1 fX 23 1 fX 218 1 fX 219 1 fX 22 1 fX 23 1 fX 800 ns 1 6 µs 52 4 ms 104 9 ms 800 ns 1 6 µs 23 1 fX 24 1 fX 219 1 fX 220 1 fX 23 1 fX 24 1 fX 1 6 µs 3 2 µs 104 9 ms 209 7 ms 1 6 µs 3 2 µs 24 1 fX 25 1 fX 220 1 fX 221 1 fX 24 1 fX 25 1 fX 3 2 µs 6 4 µs 209 7 ms 419 4 ms 3 2 µs 6 4 µs 25 1 fX 26 1 fX 221 1 fX 222 1 fX 25 1 fX 26 1 fX 6 4 µs 12 8 µs 419 4 ms 838...

Page 235: ...VENT COUNTERS Figure 9 13 Square Wave Output Operation Timing Count Clock TM1 00H 00H 00H 01H FFH 00H 01H 02H FFH 00H 01H FFH M 1 00H 00H M 01H N N N M N 1 TM2 CR10 CR20 TO2 Count Start Level Inversion Counter Clear Interval Time ...

Page 236: ... bit timer registers 1 and 2 TM1 and TM2 are started asynchronously with the count pulse Figure 9 14 8 Bit Timer Registers Start Timing 2 8 bit compare register 10 and 20 setting The 8 bit compare registers 10 and 20 CR10 and CR20 can be set to 00H Thus when these 8 bit compare registers are used as event counters one pulse count operation can be carried out When the 8 bit compare register is used...

Page 237: ...gisters 10 and 20 CR10 and CR20 are changed are smaller than those of 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the value M after CR10 and CR20 change is smaller than value N before the change it is necessary to restart the timer after changing CR10 and CR20 Figure 9 16 Timing After Compare Register Change During Timer Count O...

Page 238: ...238 MEMO ...

Page 239: ...MHz main system clock You should switch to the 32 768 kHz subsystem clock to generate 0 5 second intervals 2 Interval timer Interrupt requests INTTM3 are generated at the preset time interval Table 10 1 Interval Timer Interval Time When operated at When operated at When operated at fXX 5 0 MHz fXX 4 19 MHz fXT 32 768 kHz 24 1 fW 410 µs 488 µs 488 µs 25 1 fW 819 µs 977 µs 977 µs 26 1 fW 1 64 ms 1 9...

Page 240: ...egisters The following two types of registers are used to control the watch timer Timer clock select register 2 TCL2 Watch timer mode control register TMC2 1 Timer clock select register 2 TCL2 Refer to Figure 10 2 This register sets the watch timer count clock TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watch timer count clock T...

Page 241: ...NTTM3 To 16 Bit Timer Event Counter Watch Timer Mode Control Register TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Internal Bus TCL24 Timer Clock Select Register 2 3 fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 fW fXX 27 fXT Clear Clear Selector Selector Selector Figure 10 1 Watch Timer Block Diagram ...

Page 242: ...68 kHz fX 27 39 1 kHz fX 28 19 5 kHz Watchdog Timer Count Clock Selection 0 1 1 1 1 0 0 1 1 0 1 0 1 TCL27 TCL26 TCL25 Buzzer output disable fXX 29 fXX 210 fXX 211 Setting prohibited fX 29 9 8 kHz fX 210 4 9 kHz fX 211 2 4 kHz fX 210 4 9 kHz fX 211 2 4 kHz fX 212 1 2 kHz Buzzer Output Frequency Selection MCS 0 MCS 1 MCS 0 MCS 1 MCS 1 MCS 0 Figure 10 2 Timer Clock Select Register 2 Format Caution Wh...

Page 243: ...n enable TMC20 0 1 Normal operating mode flag set at fW 214 Fast feed operating mode flag set at fW 25 Watch Operating Mode Selection Prescaler Operation Control 5 Bit Counter Operation Control fXX 5 0 MHz Operation fXX 4 19 MHz Operation fXT 32 768 kHz Operation fXX 5 0 MHz Operation fXX 4 19 MHz Operation fXT 32 768 kHz Operation 2 Watch timer mode control register TMC2 This register sets the wa...

Page 244: ...ation The watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value The interval time can be selected with bits 4 to 6 TMC24 to TMC26 of the watch timer mode control register TMC2 Table 10 3 Interval Timer Interval Time When operated at When operated at When operated at fXX 5 0 MHz fXX 4 19 MHz fXT 32 768 kHz 0 0 0 24 1 fW 410 µs ...

Page 245: ... be generated Table 11 1 Watchdog Timer Runaway Detection Times Runaway Detection Time MCS 1 MCS 0 211 1 fXX 211 1 fX 410 µs 212 1 fX 819 µs 212 1 fXX 212 1 fX 819 µs 213 1 fX 1 64 ms 213 1 fXX 213 1 fX 1 64 ms 214 1 fX 3 28 ms 214 1 fXX 214 1 fX 3 28 ms 215 1 fX 6 55 ms 215 1 fXX 215 1 fX 6 55 ms 216 1 fX 13 1 ms 216 1 fXX 216 1 fX 13 1 ms 217 1 fX 26 2 ms 217 1 fXX 217 1 fX 26 2 ms 218 1 fX 52 4...

Page 246: ...1 fX 1 64 ms 214 1 fX 3 28 ms 214 1 fXX 214 1 fX 3 28 ms 215 1 fX 6 55 ms 215 1 fXX 215 1 fX 6 55 ms 216 1 fX 13 1 ms 216 1 fXX 216 1 fX 13 1 ms 217 1 fX 26 2 ms 217 1 fXX 217 1 fX 26 2 ms 218 1 fX 52 4 ms 219 1 fXX 219 1 fX 104 9 ms 220 1 fX 209 7 ms Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillation frequency 3 MCS Bit 0 of oscillation mode selection register...

Page 247: ... RUN WDTM3 8 Bit Counter TMMK4 RUN TMIF4 INTWDT Maskable Interrupt Request INTWDT Non Maskable Interrupt Request RESET Control Circuit 11 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 11 3 Watchdog Timer Configuration Item Configuration Timer clock select register 2 TCL2 Watchdog timer mode control register WDTM Figure 11 1 Watchdog Timer Block Diagram ...

Page 248: ...lock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the watchdog timer count clock TCL2 sets the watch timer count clock and buzzer output frequency ...

Page 249: ... 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 TCL22 TCL21 TCL20 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 fXX 29 fXX 211 fX 23 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 211 fX 24 fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 Watchdog Timer Count Clock Selection 0 1 TCL24 fXX 27 fXT 32 768 kHz fX 27 39 1 kHz fX 28 19 5 kHz Watch Timer Count Clock Selection 0 1 1 1 1 0 0 1 1 0 1 0 1 TCL27 TCL26 TCL25 ...

Page 250: ...sables counting WDTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets WDTM to 00H Figure 11 3 Watchdog Timer Mode Register Format Notes 1 Once set to 1 WDTM3 and WDTM4 cannot be cleared to 0 by software 2 The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1 3 Once set to 1 RUN cannot be cleared to 0 by software Thus once counting st...

Page 251: ... STOP mode Thus set RUN to 1 before the STOP mode is set clear the watchdog timer and then execute the STOP instruction Cautions 1 The actual runaway detection time may be shorter than the set time by a maximum of 0 5 2 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 4 Watchdog Timer Runaway Detection Time TCL22 TCL21 TCL20 Runaway Detection Ti...

Page 252: ...ute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 with the watchdog timer mode selected the interval timer mode is not set unless RESET input is applied 2 The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0 5 3 When the subsystem clock is selected for CPU clock watchdog timer count operation is stopped Table 11 5 Interval Timer I...

Page 253: ...re below to output clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled with bits 0 to 3 TCL00 to TCL03 of TCL0 2 Set the P35 output latch to 0 3 Set bit 5 PM35 of port mode register 3 to 0 set to output mode 4 Set bit 7 CLOE of TCL 0 to 1 Caution Clock output cannot be used when setting P35 output latch to 1 Remark When clock output enable disable is switched th...

Page 254: ...o types of registers are used to control the clock output function Timer clock select register 0 TCL0 Port mode register 3 PM3 1 Timer clock select register 0 TCL0 This register sets PCL output clock TCL0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TCL0 to 00H Remark Besides setting PCL output clock TCL0 sets the 16 bit timer register count clock Control register ...

Page 255: ... Valid edge specifiable 2fXX fXX fXX 2 fXX 22 Watch Timer Output INTTM3 Setting prohibited Setting prohibited fX 5 0 MHz fX 2 2 5 MHz fX 22 1 25 MHz fX 5 0 MHz fX 2 2 5 MHz fX 22 1 25 MHz fX 23 625 kHz 16 Bit Timer Register Count Clock Selection TCL00 0 1 0 1 0 1 0 1 0 MCS 1 MCS 0 MCS 1 MCS 0 PCL Output Control Figure 12 3 Timer Clock Select Register 0 Format Cautions 1 The valid edge of pin TI00 ...

Page 256: ...on with fX 5 0 MHz or fXT 32 768 kHz 2 Port mode register 3 PM3 This register set port 3 input output in 1 bit units When using the P35 PCL pin for clock output function set PM35 and output latch of P35 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 12 4 Port Mode Register 3 Format PM37 7 PM36 6 PM35 PM34 4 PM33 3 2 1 0 FF23H Address PM3 Sy...

Page 257: ... pin Follow the procedure below to output the buzzer frequency 1 Select the buzzer output frequency with bits 5 to 7 TCL25 to TCL27 of TCL2 2 Set the P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 to 0 Set to output mode Caution Buzzer output cannot be used when setting P36 output latch to 1 13 2 Buzzer Output Control Circuit Configuration The buzzer output control circuit consists...

Page 258: ...t function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Remark Besides setting the buzzer output frequency TCL2 sets the watch timer count clock and the watchdog timer count clock ...

Page 259: ...utput disable fXX 29 fXX 210 fXX 211 Setting prohibited fX 29 9 8 kHz fX 210 4 9 kHz fX 211 2 4 kHz fX 210 4 9 kHz fX 211 2 4 kHz fX 212 1 2 kHz Buzzer Output Frequency Selection 625 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz 9 8 kHz 2 4 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz 9 8 kHz 4 9 kHz 1 2 kHz MCS 1 MCS 0 MCS 1 MCS 0 MCS 1 MCS 0 Figure 13 2 Timer Clock Select Register 2 Format Ca...

Page 260: ...r ON Input mode output buffer OFF P3n Pin Input Output Mode Selection n 0 to 7 2 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P36 BUZ pin for buzzer output function set PM36 and output latch of P36 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 13 3 Port Mode Register 3 Format ...

Page 261: ... from the analog inputs ANI0 to ANI7 and execute A D conversion An A D conversion operation ends after the A D conversion operation at hardware start is completed and an interrupt request INTAD is generated In the case of software start the A D conversion operation is repeated Each time an A D conversion ends an interrupt request INTAD is generated Cautions For pins which have common functions wit...

Page 262: ...are Table 14 1 A D Converter Configuration Item Configuration Analog input 8 Channels ANI0 to ANI7 A D converter mode register ADM Control register A D converter input select register ADIS External interrupt mode register 1 INTM1 Successive approximation register SAR A D conversion result register ADCR Register ...

Page 263: ...13 ANI4 P14 ANI5 P15 ANI6 P16 ANI7 P17 Selector A D Converter Mode Register 3 Trigger Enable ES40 ES41 Sample Hold Circuit 3 CS ADIS3 4 Internal Bus Internal Bus Edge Detector Control Circuit Series Resistor String AVDD Voltage Comparator Tap Selector INTAD INTP3 Successive Approximation Register SAR A D Converter Input Select Register ADIS2 ADIS1 ADIS0 Note 1 Note 2 ADM1 to ADM3 INTP3 P03 TRG FR1...

Page 264: ...t voltage 5 Series resistor string The serial resistance string is connected between AVREF0 and AVSS and generates voltages which are compared to analog inputs 6 ANI0 to ANI7 pins These are 8 channel analog input pins to input analog signals to undergo A D conversion to the A D converter Pins other than those selected as analog input by the A D converter input select register ADIS can be used as i...

Page 265: ...between the AVREF0 pin and the AVSS pin causing a large reference voltage error 8 AVSS pin This is a GND potential pin of the A D converter Keep it at the same potential as the VSS pin when not using the A D converter 9 AVDD pin This is an A D converter analog power supply pin Keep it at the same potential as the VDD pin when not using the A D converter 14 3 A D Converter Control Registers The fol...

Page 266: ...2 1 0 FF80H Address ADM Symbol ADM2 ADM1 HSC 5 01H After Reset R W R W ADM3 0 0 0 0 1 1 1 1 ADM2 0 0 1 1 0 0 1 1 ADM1 0 1 0 1 0 1 0 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 TRG 0 1 No external trigger software starts Conversion started by external trigger hardware starts FR1 0 0 1 1 FR0 0 1 0 0 Other than above 80 fX Setting prohibited Note 2 40 fX Setting prohibited Note 2 50 fX Setting prohibit...

Page 267: ...input with ADIS 2 No internal pull up resistor can be used to the channels set for analog input with ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option register L PUOL Figure 14 3 A D Converter Input Select Register Format 0 7 0 6 0 0 4 ADIS3 3 2 1 0 FF84H Address ADIS Symbol ADIS2 ADIS1 ADIS0 5 00H After Reset R W R W ADIS3 0 0 0 0 0 0 0 0 1 Other than above Number of Ana...

Page 268: ... 0 0 1 1 ES60 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges ES71 0 0 1 1 ES70 0 1 0 1 Falling edge Rising edge Setting prohibited Both falling and rising edges INTP3 Valid Edge Selection INTP4 Valid Edge Selection INTP5 Valid Edge Selection INTP6 Valid Edge Selection 3 External interrupt mode register 1 INTM1 This register sets the valid edge for INTP3 to INTP6 ...

Page 269: ... s voltage tap and the analog input is compared by the voltage comparator If the analog input is greater than 1 2 AVREF0 the MSB of SAR remains set as is Also if it is less than 1 2 AVREF0 the MSB is reset 7 Next bit 6 of SAR is automatically set and the operation proceeds to the next comparison In this case the series resistor string voltage tap is selected according to the preset value of bit 7 ...

Page 270: ... Result Figure 14 5 A D Converter Basic Operation A D conversion operations are performed continuously until bit 7 CS of ADM is reset 0 by software If a write to the ADM is performed during an A D conversion operation the conversion operation is initialized and if the CS bit is set 1 conversion starts again from the beginning After RESET input the value of ADCR is undefined ...

Page 271: ...ersion result the value stored in A D conversion result register ADCR is shown by the following expression ADCR INT 256 0 5 or ADCR 0 5 VIN ADCR 0 5 Where INT Function which returns integer parts of value in parentheses VIN Analog input voltage AVREF0 AVREF0 pin voltage ADCR Value of A D conversion result register ADCR Figure 14 6 shows the relation between the analog input voltage and the A D con...

Page 272: ...er mode register ADM are set to 1 the A D conversion standby state is set When the external trigger signal INTP3 is input the A D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 ADM1 to ADM3 of ADM Upon termination of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is g...

Page 273: ... of the A D conversion the conversion result is stored in the A D conversion result register ADCR and the interrupt request signal INTAD is generated After one A D conversion operation is started and terminated the next A D conversion operation starts immediately The A D conversion operation con tinues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again dur...

Page 274: ...by mode However there is no precision to the actual AVREF0 voltage and therefore the conversion values themselves lack precision and can only be used for relative comparison Figure 14 9 Example of Method of Reducing Current Consumption in Standby Mode 2 Input range of ANI0 to ANI7 The input voltages of ANI0 to ANI7 should be within the specification range In particular if a voltage above AVREF0 or...

Page 275: ...tion for port 1 during conversion as this could lower the conversion resolution Also if digital pulses are applied to a pin adjacent to the pin in the process of A D conversion the expected A D conversion value may not be obtainable due to coupling noise Therefore avoid applying pulses to pins adjacent to the pin undergoing A D conversion 5 AVREF0 pin input impedance A series resistor string of ap...

Page 276: ... changed Caution is therefore required since if a change of analog input pin is performed during A D conversion the A D conversion result and ADIF for the analog input before the change may be set just before the ADM rewrite If ADIF is read immediately after the ADM rewrite ADIF will be set regardless of whether A D conversion of the analog input after the change has been completed When the A D co...

Page 277: ...eparately to VDD and AVDD and connect separate grounds to VSS and AVSS 8 Port Operations Among A D Converter Operations For pins which have common functions with a port See 3 1 1 or 4 1 1 Normal operating mode pins 1 Port pins do not execute the following operations during A D conversion If performed then the general error standards cannot be maintained during A D conversion 1 If it is used as a p...

Page 278: ...278 MEMO ...

Page 279: ...D A conversion is started by setting the DACE0 and DACE1 of the D A converter mode register DAM There are two types of modes for the D A converter as follows 1 Normal mode Outputs an analog voltage signal immediately after the D A conversion 2 Real time output mode Outputs an analog voltage signal synchronously with the output trigger after the D A conversion Since a sine wave can be generated in ...

Page 280: ... A conversion value set register 1 DACS1 Control register D A converter mode register DAM Figure 15 1 D A Converter Block Diagram Register Selector D A Conversion Value Set Register 1 DACS1 Internal Bus Internal Bus 2R 2R 2R 2R R R 2R 2R 2R 2R R R DAM5 ANO1 P131 ANO0 P130 D A Converter Mode Register DACS1 Write INTTM2 DACS0 Write INTTM1 AVREF1 AVSS D A Conversion Value Set Register 0 DACS0 DAM4 DA...

Page 281: ...T input sets these registers to 00H Analog voltage output to the ANO0 and ANO1 pins is determined by the following expression ANOn output voltage AVREF1 where n 0 1 Cautions 1 In the real time output mode when data that are set in DACS0 and DACS1 are read before an output trigger is generated the previous data are read rather than the set data 2 In the real time output mode data should be set to D...

Page 282: ...D A Converter Control Registers The D A converter mode register DAM controls the D A converter This register sets D A converter operation enable stop The DAM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 15 2 D A Converter Mode Register Format Cautions 1 When using the D A converter a dual function port pin should be set to the input mode...

Page 283: ... start A D conversion operation for channels 0 and 1 by setting bits 0 and 1 DACE0 DACE1 of DAM 4 After D A conversion when in the normal mode analog voltages are output immediately to pins ANO0 P130 and ANO1 P131 When in the real time output mode analog voltages are output in sync with the output trigger 5 In the normal mode the analog voltage signals to be output are held until new data are set ...

Page 284: ...ample of Buffer Amplifier a Inverting amplifier b Voltage follower 2 Output voltage of D A converter Because the output voltage of the converter changes in steps use the D A converter output signals in general by connecting a low pass filter 3 AVREF1 pin When only either one of the D A converter channels is used with AVREF1 VDD the pin that is not used as an analog output must be set as follows Se...

Page 285: ...22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Serial transfer end interrupt request flag CSIIF0 Channel 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Automatic transmit receive function Serial transfer end interrupt request flag CSIIF1 Channel 2 Baud rate generator ...

Page 286: ...ntrollers that incorporate a conventional synchronous clocked serial interface as is the case with the 75X XL 78K and 17K series 3 SBI serial bus interface mode MSB first This mode is used for 8 bit data transfer with two or more devices using two lines of serial clock SCK0 and serial data bus SB0 or SB1 The SBI mode is compatible with the NEC Serial Bus Format and sends and receives data distingu...

Page 287: ...ope with any one of the possible data transfer formats by controlling the SCK0 level and the SB0 or SB1 output level Thus the handshake line previously necessary for connection of two or more devices can be removed resulting in the increased number of available input output ports Figure 16 1 Serial Bus Interface SBI System Configuration Example Master CPU SCK0 SB0 SCK0 SB0 Slave CPU1 SCK0 SB0 Slav...

Page 288: ...nel 0 Configuration Item Configuration Serial I O shift register 0 SIO0 Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Control register Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Note Register Note See Figure 6 5 P20 P21 P23 to P26 Block Diagram and Figure 6 6 P22 and P27 Block Dia...

Page 289: ...ase Command Acknowledge Detector Serial Clock Counter Serial Clock Control Circuit CLR D SET Q Match Busy Acknowledge Output Circuit Interrupt Request Signal Generator ACKD CMDD RELD WUP Selector Selector TCL33 TCL32 TCL31 TCL30 4 Timer Clock Select Register 3 fxx 2 to fxx 28 INTCSI0 CLD SIC SVAM CSIM01 CSIM00 CSIM01 CSIM00 Slave Address Register SVA SVAM Serial Bus Interface Control Register Seri...

Page 290: ...e SVA is set with an 8 bit memory manipulation instruction The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the slave address output from the master device and the SVA value are compared with an address comparator If they match the slave device has been selected In that case bit 6 COI of serial operating mode register...

Page 291: ...gnal generation It generates the interrupt request signal in the following cases In the 3 wire serial I O mode and 2 wire serial I O mode This circuit generates an interrupt request signal every eight serial clocks In the SBI mode When WUPNote is 0 Generates an interrupt request signal every eight serial clocks When WUPNote is 1 Generates an interrupt request signal when the serial I O shift regis...

Page 292: ...serial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus interface control register SBIC Interrupt timing specify register SINT 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H ...

Page 293: ...0 1 1 0 0 0 1 0 1 0 1 0 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 Setting prohibited fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz Other than above Setting prohibited 6 5 4 3 2 1 0 7 Symbol TCL3 TCL37 TCL36 TCL35 ...

Page 294: ...PXX Port Output Latch SBI mode 6 5 4 3 2 1 0 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off chip 8 bit timer register 2 TM2 output 0 0 SCK0 CMOS input output R W 1 Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM 04 0 1 CSIM00 0 1 FF60H 00H R WNote 1 Address After Rese...

Page 295: ...l to serial I O shift register 0 SIO0 data Slave address register SVA equal to serial I O shift register 0 SIO0 data R CSIE0 0 1 Serial Interface Channel 0 Operation ControlNote 3 Operation stopped Operation enable R W Figure 16 4 Serial Operating Mode Register 0 Format 2 2 Notes 1 To use the wake up function WUP 1 clear the bit 5 SIC of the interrupt timing specify register SINT to 0 2 When CSIE0...

Page 296: ... Address After Reset R W CMDT Used for command signal output When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W R RELD Bus Release Detection Set Conditions RELD 1 Clear Conditions RELD 0 When bus release signal REL is detected When transfer start instruction is executed If SIO0 and SVA values do not match in address recepti...

Page 297: ...dge of SCK0 just after execution of the instruction to be set to 1 automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output After completion of transfer 1 R W R ACKD Acknowledge Detection Clear Conditions ACKD 0 Falling edge of the SCK0 immediately after the busy mode is released while executing the transfer start instruction When CSIE0 0 When RESET i...

Page 298: ...ake up function in the SBI mode set SIC to 0 3 When CSIE0 0 CLD becomes 0 Remark SVA Slave address register CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of Serial Operation Mode Register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R WNote 1 Address After Reset R W SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 SIC 0 INTCSI0 Inter...

Page 299: ... 3 wire serial I O mode SBI mode 2 wire serial I O mode 16 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 0 SIO0 does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SI0 SB0 P26 SO0 SB1 and P27 SCK0 pins can be used as...

Page 300: ...erial interface as is the case with the 75X XL 78K and 17K Series Communication is carried out with three lines of serial clock SCK0 serial output SO0 and serial input SI0 1 Register setting The 3 wire serial I O mode is set with serial operating mode register 0 CSIM0 and the serial bus interface control register SBIC a Serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memo...

Page 301: ...upt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the slave address register SVA data in SBI mode R W 1 MSB LSB 1 0 0 0 1 Note 2 3 wire serial l O mode SI0 Input SO0 CMOS output SCK0 CMOS input output 2 wire serial I O mode see section 16 4 4 2 wire serial I O mode operation 1...

Page 302: ...leared to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W b Serial bus interface control register SBIC SBIC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SBIC to 00H CSIE0 Bit 7 of Serial Operation Mode Registe...

Page 303: ...and is output from the SO0 pin The received data input to the SI0 pin is latched in SIO0 at the rising edge of SCK0 Upon termination of 8 bit transfer SIO0 operation stops automatically and the interrupt request flag CSIIF0 is set Figure 16 7 3 Wire Serial I O Mode Timings The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses Thus the SO0 pin output status can be manipulated by s...

Page 304: ...ister 0 CSIM0 Figure 16 9 Circuit of Switching in Transfer Bit Order Start bit switching is realized by switching the bit order for data write to SIO0 The SIO0 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to SIO0 5 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIO0 when the...

Page 305: ...the application program which controls serial interface channel 0 can be simplified The SBI function is incorporated into various devices including 75X XL Series and 78K Series Figure 16 10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI and peripheral ICs are used In SBI the SB0 SB1 serial data bus pin is an open drain output pin and therefore the ...

Page 306: ...functions are described below a Address command data identify function Serial data is distinguished into addresses commands and data b Chip select function by address transmission The master executes slave chip selection by address transmission c Wake up function The slave can easily judge address reception chip select judgement with the wake up function which can be set or cleared by the software...

Page 307: ... The dotted line indicates READY status The bus release signal and the command signal are output by the master device BUSY is output by the slave signal ACK can be output by either the master or slave device normally the 8 bit data receiver outputs Serial clocks continue to be output by the master device from 8 bit data transfer start to BUSY reset SCK0 SB0 SB1 SCK0 SB0 SB1 SCK0 SB0 SB1 8 9 9 A7 A...

Page 308: ...ity this may be judged to be a bus release signal even though data is being sent Thus much care is requiring in wiring b Command signal CMD The command signal is a signal with the SB0 SB1 line which has changed from the high level to the low level when the SCK0 line is at the high level without serial clock output This signal is output by the master device Figure 16 13 Command Signal The command s...

Page 309: ...ed to the bus line in order to select a particular slave device Figure 16 14 Addresses 8 bit data following bus release and command signals is defined as an address In the slave device this condition is detected by hardware and whether or not 8 bit data matches the own specification number slave address is checked by hardware If the 8 bit data matches the slave address the slave device has been se...

Page 310: ...n Figure 16 16 Commands Figure 16 17 Data 8 bit data following a command signal is defined as command data 8 bit data without command signal is defined as data Command and data operation procedures are allowed to determine by user according to communications specifications SCK0 C7 C6 C5 C4 C3 C2 C1 C0 1 2 3 4 5 6 7 8 SB0 SB1 Command Command Signal SCK0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 SB0 S...

Page 311: ...nization with 9th clock SCK0 Remark The dotted line indicates READY status The acknowledge signal is one shot pulse to be generated at the falling edge of SCK0 after 8 bit data transfer It can be positioned anywhere and can be synchronized with any clock SCK0 After 8 bit data transmission the transmitter checks whether the receiver has returned the acknowledge signal If the acknowledge signal is n...

Page 312: ... edge of SCK0 When the BUSY signal is reset the master device automatically terminates the output of SCK0 serial clock When the BUSY signal is reset and the READY signal is set the master device can start the next transfer Caution In SBI after specifying reset of BUSY the BUSY signal is output until the fall of the next serial clock If WUP 1 is set during this interval by mistake it will be imposs...

Page 313: ...Address After Reset R W R W CSIM 03 CSIM 02 PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SI0 SB0 P25 Pin Function SO0 SB1 P26 Pin Function SCK0 P27 Pin Function 1 0 0 0 0 0 0 0 1 1 Note 2 Note 2 Note 2 Note 2 MSB P25 CMOS input output SB0 N ch open drain input output SB1 N ch open drain input output P26 CMOS input output WUP 0 1 Wake up Function Control Note 3 Interrupt request signal gener...

Page 314: ...n is executed If SIO0 and SVA values do not match in address reception only when WUP 1 When CSIE0 0 When RESET input is applied R CMDD Command Detection Clear Conditions CMDD 0 When transfer start instruction is executed When bus release signal REL is detected When CSIE0 0 When RESET input is applied Set Conditions CMDD 1 When command signal CMD is detected Acknowledge signal is output in synchron...

Page 315: ...etected at the rising edge of SCK0 clock after completion of transfer BSYE Synchronizing Busy Signal Output Control 0 Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after execution of the instruction to be cleared to 0 sets READY status R W Note 1 Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal Note Busy mode ...

Page 316: ... detection or termination of serial interface channel 0 transfer CLD 0 1 SCK0 P27 Pin LevelNote 3 Low level High level R W R W R 1 c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Caution Be sure to set bits 0 to 3 to 0 Notes 1 Bit 6 CLD is a read only bit 2 When using wake up function in the SBI mode set SIC to...

Page 317: ...6 A1 A0 ACK Slave Address When Addresses Match When Addresses do not Match SCK0 SB0 SB1 RELT CMDT CMDD RELD SIO0 Slave address write to SIO0 Transfer Start Instruction 4 Various signals Figures 16 20 to 16 25 show various signals and flag operations in SBI Table 16 3 lists various signals in SBI Figure 16 20 RELT CMDT RELD and CMDD Operations Master Figure 16 21 RELT and CMDD Operations Slave ...

Page 318: ...L 0 µPD78058F SUBSERIES SCK0 6 SB0 SB1 ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output for a period of one clock just after setting Figure 16 22 ACKT Operation Caution Do not set ACKT before termination of transfer ...

Page 319: ...put SCK0 Figure 16 23 ACKE Operations a When ACKE 1 upon completion of transfer b When set after completion of transfer c When ACKE 0 upon completion of transfer d When ACKE 1 period is short SB0 SB1 ACKE 7 8 9 D1 D0 ACK 6 D2 If set during this period and ACKE 1 at the falling edge of the next SCK0 ACK signal is output for a period of one clock just after setting SCK0 SB0 SB1 ACKE 1 2 7 8 9 D7 D6 ...

Page 320: ...2 D0 Transfer Start Instruction Transfer Start SCK0 Figure 16 24 ACKD Operations a When ACK signal is output at 9th clock of SCK0 b When ACK signal is output after 9th clock of SCK0 c Clear timing when transfer start is instructed in BUSY Figure 16 25 BSYE Operation SCK0 SB0 SB1 ACKD 7 8 9 D1 D0 ACK 6 D2 Transfer Start Instruction SIO0 Transfer Start SCK0 SB0 SB1 ACKD ACK 9 Transfer Start Instruct...

Page 321: ...d of SCK0 after completion of serial reception Synchronous BUSY signal Low level signal to be output to SB0 SB1 following Acknowledge signal Master slave 1 BSYE 0 2 Execution of instruction for data write to SIO0 transfer start instruction SB0 SB1 rising edge when SCK0 1 Master Bus release signal REL RELT set RELD set CMDD clear CMDD set CMDT set Master Command signal CMD SB0 SB1 falling edge when...

Page 322: ...dress value of slave device on the serial bus Address A7 to A0 8 bit data to be transferred in synchronization with SCK0 after output of REL and CMD signals Master Commands C7 to C0 Instructions and messages to the slave device Master slave Data D7 to D0 8 bit data to be transferred in synchronization with SCK0 without output of REL and CMD signals Table 16 3 Various Signals in SBI Mode 2 2 When C...

Page 323: ...stor is necessary Figure 16 26 Pin Configuration Caution When receiving data it is necessary to set the N ch open drain output in the high impedance state so please write FFH in serial I O shift register 0 SIO0 in advance This will keep it in the high impedance state at all times during transmission However in the case of the wake up function instruction bit WUP 1 the N ch open drain output is alw...

Page 324: ...ansmitted is fetched into the destination device that is the serial I O shift register 0 SIO0 Thus transmit errors can be detected in the following way a Method of comparing SIO0 data before transmission to that after transmission In this case if two data differ from each other a transmit error is judged to have occurred b Method of using the slave address register SVA Transmit data is set to both...

Page 325: ... Program Processing CMDD Set INTCSI0 Generation ACK Output Hardware Operation CMDT Set RELT Set CMDT Set Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver CMDD Clear CMDD Set RELD Set Serial Reception BUSY Output READY When SVA SIO0 Address BUSY Clear BUSY Clear Figure 16 27 Address Transmi...

Page 326: ...peration ACKT Set Program Processing INTCSI0 Generation ACK Output Hardware Operation CMDT Set Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver CMDD Set Serial Reception BUSY Output READY Command BUSY Clear BUSY Clear SIO0 Read Command analysis Figure 16 28 Command Transmission from Master...

Page 327: ... SCK0 Stop Hardware Operation ACKT Set Program Processing INTCSI0 Generation ACK Output Hardware Operation Write to SIO0 Interrupt Servicing Preparation for the Next Serial Transfer Master Device Processing Transmitter Transfer Line Slave Device Processing Receiver Serial Reception BUSY Output READY Data BUSY Clear BUSY Clear SIO0 Read Figure 16 29 Data Transmission from Master Device to Slave Dev...

Page 328: ...Operation Program Processing INTCSI0 Generation ACKD Set Hardware Operation FFH Write to SIO0 Master Device Processing Receiver Transfer Line Slave Device processing Transmitter Serial Transmission BUSY Output READY Data BUSY Clear Write to SIO0 SCK0 Stop BUSY Clear 1 2 READY BUSY D7 D6 ACKT Set SIO0 Read Receive data processing FFH Write to SIO0 Write to SIO0 Figure 16 30 Data Transmission from S...

Page 329: ...e up function instruction bit WUP 1 the N ch open drain output is always in the high impedance state so it is not necessary to write FFH in SIO0 before reception 3 If data is written to SIO0 when the slave is busy the data is not lost When the busy state is cleared and SB0 or SB1 input is set to the high level READY state transfer starts Upon termination of 8 bit transfer serial transfer automatic...

Page 330: ...o so by means of transmission reception of the command preset by program instead of using the address match detection method c In SBI after specifying reset of BUSY the BUSY signal is output until the fall of the next serial clock If WUP 1 is set during this interval by mistake it will be impossible to reset BUSY Therefore after resetting the BUSY signal confirm that the level of the SB0 SB1 pin h...

Page 331: ...input output SB0 or SB1 Figure 16 31 Serial Bus Configuration Example Using 2 Wire Serial I O Mode 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIM0 serial bus interface control register SBIC and interrupt timing specify register SINT a Serial operating mode register 0 CSIM0 CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET ...

Page 332: ...CMDD RELD 1 matches the slave address register SVA data in SBI mode R W 2 wire serial l O mode 0 1 1 1 0 0 0 0 0 0 1 1 Note 2 Note 2 Note 2 Note 2 MSB P25 CMOS input output SB0 N ch open drain input output SB1 N ch open drain input output P26 CMOS input output 3 wire Serial I O mode see section 16 4 2 3 wire serial I O mode operation SBI mode see section 16 4 3 SBI mode operation Note 3 COI 0 Slav...

Page 333: ...0 Bit 7 of Serial Operation Mode Register 0 CSIM0 c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Caution Be sure to set bits 0 to 3 to 0 Notes 1 Bit 6 CLD is a read only bit 2 When CSIE0 0 CLD becomes 0 Remark CSIIF0 Interrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of Serial Operation Mode Register ...

Page 334: ...he interrupt request flag CSIIF0 is set Figure 16 32 2 Wire Serial I O Mode Timings Since the SB0 SB1 pin specified in the serial data bus is an N ch open drain input output it is necessary for it to be pulled up externally Also it is necessary for the N ch open drain output to be set in the high impedance state when receiving data so write FFH in SIO0 in advance The SB0 or SB1 pin generates the S...

Page 335: ...ance Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF0 is set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIO0 Thus transmit error can be detected in the following way a Method of comparing SIO0 data before transmi...

Page 336: ...put is also possible by software in addition to normal serial clock output P27 output latch manipulation enables any value of SCK0 to be set by software SI0 SB0 and SO0 SB1 pin to be controlled with the RELT and CMDT bits of serial bus interface control register SBIC SCK0 P27 pin output manipulating procedure is described below 1 Set the serial operating mode register 0 CSIM0 SCK0 pin enabled for ...

Page 337: ...fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Serial transfer end interrupt request flag CSIIF0 Channel 1 fXX 2 fXX 22 fXX 23 fXX 24 fXX 25 fXX 26 fXX 27 fXX 28 external clock TO2 output MSB LSB switchable as the start bit Automatic transmit receive function Serial transfer end interrupt request flag CSIIF1 Channel 2 Baud rate generator out...

Page 338: ...0 and serial input SI0 This mode enables simultaneous transmission reception and therefore reduces the data transfer processing time The start bit of transferred 8 bit data is switchable between MSB and LSB so that devices can be connected regardless of their start bit recognition This mode should be used when connecting with peripheral I O devices or display controllers which incorporate a conven...

Page 339: ...with the I2C bus format In this mode the transmitter outputs three kinds of data onto the serial data bus start condition data and stop condition to be actually sent or received The receiver automatically distinguishes the received data into start condition data or stop condition by hardware Figure 17 1 Serial Bus Configuration Example Using I2C Bus Master CPU SCL SDA0 SDA1 SCL SDA0 SDA1 Slave CPU...

Page 340: ...nel 0 Configuration Item Configuration Serial I O shift register 0 SIO0 Slave address register SVA Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Control register Serial bus interface control register SBIC Interrupt timing specify register SINT Port mode register 2 PM2 Note Note See Figure 6 7 P20 P21 P23 to P26 Block Diagram and Figure 6 8 P22 and P27 Block Diagram Regi...

Page 341: ...D RELD CMDT RELT Internal Bus Stop Condition Start Condition Acknowledge Detector Serial Clock Counter Serial Clock Control Circuit CLR D SET Q Match Acknowledge Output Circuit Interrupt Request Signal Generator ACKD CMDD RELD WUP Selector Selector TCL33 TCL32 TCL31 TCL30 4 Timer Clock Select Register 3 fxx 2 to fxx 28 INTCSI0 CLD SIC SVAM BSYE CLC WREL WAT1 WAT0 CSIM01 CSIM00 TO2 1 16 Divider CSI...

Page 342: ...Wake up function 2 Slave address register SVA This is an 8 bit register to set the slave address value for connection of a slave device to the serial bus This register is not used in the 3 wire serial I O mode SVA is set with an 8 bit memory manipulation instruction The master device outputs a slave address for selection of a particular slave device to the connected slave device These two data the...

Page 343: ... register 0 SIO0 When the internal system clock is used the circuit also controls clock output to the SCK0 SCL P27 pin 6 Interrupt signal generator This circuit controls interrupt request signal generation It generates interrupt request signals according to the settings of interrupt timing specification register SINT bits 0 and 1 WAT0 WAT1 and serial operation mode register 0 CSIM0 bit 5 WUP as sh...

Page 344: ...rmation is generated by the receiving side thus ACKE should be set to 0 disable Other than above Setting prohibited I2C bus mode receive 1 0 1 0 0 An interrupt request signal is generated each time 8 serial clocks are counted 8 clock wait ACK information is output by manipulating ACKT by software after an interrupt request is generated 1 1 0 1 An interrupt request signal is generated each time 9 s...

Page 345: ...serial interface channel 0 Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Serial bus interface control register SBIC Interrupt timing specify register SINT 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 0 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H ...

Page 346: ... kHz fX 27 39 1 kHz fX 28 19 5 kHz MCS 0 fX 22 1 25 MHz fX 23 625 kHz fX 24 313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz Other than above Setting prohibited 6 5 4 3 2 1 0 7 Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 88H R W Address After Reset R W MCS 0 fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 77 kHz fX 210 4 88 kHz fX 211 2 44...

Page 347: ...enable stop wake up function and displays the address comparator match signal CSIM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM0 to 00H Caution Do not switch the operating mode 3 wire serial I O 2 wire serial I O I2C bus while operation of serial interface channel 0 is enabled The operation mode should be switched after stopping the serial operation ...

Page 348: ...ote 1 Address After Reset R W R W CSIM 03 CSIM 02 PM25 P25 PM26 P26 PM27 P27 Operation Mode Start Bit SI0 SB0 SDA0 P25 Pin Function SO0 SB1 SDA1 P26 Pin Function SCK0 SCL P27 Pin Function 1 MSB LSB 1 0 0 0 1 Note 3 3 wire serial l O mode SI0 Input SO0 CMOS output SCK0 CMOS input output Note 3 2 wire serial l O mode or I2 C Bus Mode 0 SCK0 SCL N ch open drain input output 1 1 1 0 0 0 0 0 0 1 1 Note...

Page 349: ... W CMDT Used for start condition signal output When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W R RELD Stop Condition Detection Set Conditions RELD 1 Clear Conditions RELD 0 When stop condition signal is detected When transfer start instruction is executed If SIO0 and SVA values do not match in address reception When CSIE...

Page 350: ...put However output with ACKT is enabled Used for reception when 8 clock wait mode is selected or for transmission Note 2 Enables acknowledge signal automatic output Outputs acknowledge signal in synchronization with the falling edge of the 9th SCL clock cycle automatically output when ACKE 1 However not automatically cleared to 0 after acknowledge signal output Used in reception with 9 clock wait ...

Page 351: ...when the state is cancelled Used to cancel wait state by means of WAT0 and WAT1 CLC 0 1 Clock Level Control Note 2 Used in I2 C bus mode Make output level of SCL pin low unless serial transfer is being performed R W 1 Wait Sate Cancellation Control R W WAT1 0 1 Wait and Interrupt Control Generates interrupt service request at rising edge of 8th SCK0 clock cycle keeping clock output in high impedan...

Page 352: ...terrupt request flag corresponding to INTCSI0 CSIE0 Bit 7 of Serial Operation Mode Register 0 CSIM0 SVAM 0 1 SVA Bit to be Used as Slave Address Bits 0 to 7 Bits 1 to 7 SIC 0 INTCSI0 Interrupt Source SelectionNote1 CSIIF0 is set to 1 upon termination of serial interface channel 0 transfer CSIIF0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer CLD 0 1...

Page 353: ... I O mode 2 wire serial I O mode I2C Inter IC bus mode 17 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 0 SIO0 does not carry out shift operation either and thus it can be used as ordinary 8 bit register In the operation stop mode the P25 SI0 SB0 SDA0 P26 SO0 SB1 SDA1 and P27 SCK0 SCL pins c...

Page 354: ...atch 6 5 4 3 2 1 0 7 Symbol CSIM0 CSIE0 COI WUP CSIM04 CSIM03 CSIM02 CSIM01 CSIM00 CSIM01 0 1 Serial Interface Channel 0 Clock Selection Input Clock to SCK0 pin from off chip 8 bit timer register 2 TM2 output 0 2 wired serial I O mode see the section 17 4 3 2 wire serial I O mode operation R W 1 Clock specified with bits 0 to 3 of timer clock select register 3 TCL3 CSIM 04 0 CSIM00 0 1 FF60H 00H R...

Page 355: ... 3 2 1 0 7 Symbol SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT RELT When RELT 1 SO0 Iatch is set to 1 After SO0 Iatch setting automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W FF61H 00H R W Address After Reset R W CMDT When CMDT 1 SO0 Iatch is cleared to 0 After SO0 latch clearance automatically cleared to 0 Also cleared to 0 when CSIE0 0 R W CSIE0 Bit 7 of Serial Operation Mode Regist...

Page 356: ...d is output from the SO0 pin The received data input to the SI0 pin is latched in SIO0 at the rising edge of SCK0 Upon termination of 8 bit transfer SIO0 operation stops automatically and the interrupt request flag CSIIF0 is set Figure 17 7 3 Wire Serial I O Mode Timings The SO0 pin is a CMOS output pin and outputs current SO0 latch statuses Thus the SO0 pin output status can be manipulated by set...

Page 357: ... CSIM0 Figure 17 9 Circuit of Switching in Transfer Bit Order Start bit switching is realized by switching the bit order for data write to SIO0 The SIO0 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to the shift register 5 Transfer start Serial transfer is started by setting transfer data to the serial I O shift register 0 SIO0 w...

Page 358: ...ally carried out with two lines of serial clock SCK0 and serial data input output SB0 or SB1 Figure 17 10 Serial Bus Configuration Example Using 2 Wire Serial I O Mode 1 Register setting The 2 wire serial I O mode is set with the serial operating mode register 0 CSIM0 serial bus interface control register SBIC and interrupt timing specify register SINT Master SCK0 Slave SB0 SB1 SCK0 SB0 SB1 AVDD A...

Page 359: ...peration Mode Start Bit SIO SB0 SDA0 P25 Pin Function SO0 SB1 SDA1 P26 Pin Function SCK0 SCL P27 Pin Function WUP 0 1 Wake up Function ControlNote 3 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the address received after detecting start condition when CMDD 1 matches the slave address register SVA data in I2 C bus mode R W 2 wire...

Page 360: ...00H CSIE0 Bit 7 of Serial Operation Mode Register 0 CSIM0 c Interrupt timing specify register SINT SINT is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets SINT to 00H Notes 1 Bit 6 CLD is a read only bit 2 When CSIE0 0 CLD becomes 0 Caution Be sure to set bits 0 to 3 to 0 in the 2 wire serial I O mode is used CSIIF0 Interrupt request flag corresponding to INTCSI0 6 5 4 3...

Page 361: ...shift register at the rising edge of SCK0 Upon termination of 8 bit transfer the shift register operation stops automatically and the interrupt request flag CSIIF0 is set Figure 17 11 2 Wire Serial I O Mode Timings Pin SB0 or SB1 specified in the serial data bus is an N ch open drain input and output so it is necessary to pull it up externally It is also necessary to set the N ch open drain output...

Page 362: ...vance Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF0 is set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIO0 Thus transmit error can be detected in the following way a Method of comparing SIO0 data before transm...

Page 363: ...ication the master sends start condition data and stop condition signals to slave devices through the serial data bus while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware This simplifies the application program controlling the I2C bus An example of a serial bus configuration is shown in Figure 17 13 This system b...

Page 364: ...e I2C bus can perform independ ent operations during the serial communication d Acknowledge signal ACK control function The master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally e Wait signal WAIT control function When a slave device is preparing for data transmission or reception and requires more waiting time the...

Page 365: ...al are defined as an address The 7 bit address data is output by the master device to specify a specific slave from among those connected to the bus line Each slave device on the bus line must therefore have a different address Therefore after a slave device detects the start condition it compares the 7 bit address data received and the data of the slave address register SVA After the comparison o...

Page 366: ...sending side that has tranferred 8 bit data waits for the acknowledge signal which will be sent from the receiving side If the sending side device receives the acknowledge signal which means a success ful data transfer it proceeds to the next processing If this signal is not sent back from the slave device this means that the data sent has not been received by the slave device and therefore the ma...

Page 367: ...ng operation of slave devices see section 17 4 5 Cautions on Use of I2C Bus Mode Figure 17 20 Wait Signal a Wait of 8 Clock Cycles b Wait of 9 Clock Cycles SCL of Master Device D2 D1 D0 ACK D7 Output by manipulating ACKT 6 7 8 9 1 3 2 4 D6 D5 D4 Set low because slave device drives low though master device returns to Hi Z state No wait is inserted after 9th clock cycle and before master device star...

Page 368: ...rial I O or N ch open CMOS I O N ch open I2C bus mode drain I O drain I O R W WUP Wake up Function ControlNote 4 0 Interrupt request signal generation with each serial transfer in any mode 1 In I2C bus mode interrupt request signal is generated when the address data received after start condition detection when CMDD 1 matches data in slave address SVA register R COI Slave Address Comparison Result...

Page 369: ... started R W ACKE Acknowledge Signal Automatic Output ControlNote 2 0 Disabled with ACKT enabled Used when receiving data in the 8 clock wait mode or when transmitting data Note 3 1 Enabled After completion of transfer acknowledge signal is output in synchronization with the 9th falling edge of SCL clock automatically output when ACKE 1 However not automatically cleared to 0 after acknowl edge sig...

Page 370: ...Releases the wait state Automatically cleared to 0 after releasing the wait state This bit is used to release the wait state set by means of WAT0 and WAT1 R W CLC Clock Level Control 0 Used in I2C bus mode In cases other than serial transfer SCL pin output is driven low 1 Used in I2C bus mode In cases other than serial transfer SCL pin output is set to high impedance Clock line is held high Used b...

Page 371: ...SIIF0 Also see Note 3 below Address A6 to A0 Definition 7 bit data synchronized with SCL immediately after start condition signal Function Indicates address value for specification of slave on serial bus Signaled by Master Signaled when See Note 2 below Affected flag s CSIIF0 Also see Note 3 below Transfer direction R W Definition 1 bit data output in synchronization with SCL after address output ...

Page 372: ...s set do not write FFH in SIO0 before reception Even if FFH is not written in SIO0 the N ch open drain output is always in the high impedance state 6 Address match detection method In the I2C mode the master can select a specific slave device by sending slave address data CSIIF0 is set if the slave address transmitted by the master coincides with the value set to the slave address register SVA whe...

Page 373: ...nization with the falling edge of the serial clock SCL the SO0 latch outputs the data on an MSB first basis from the SDA0 or SDA1 pin to the receiving device In the receiving device the data input from the SDA0 or SDA1 pin is taken into the SIO0 in synchroniza tion with the rising edge of SCL 9 Start of transfer A serial transfer is started by setting transfer data in serial I O shift register 0 S...

Page 374: ...L L 1 A5 A4 A3 A2 A1 A0 W ACK A6 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 1 2 3 4 5 9 L L L L L SIO0 Address Master Device Operation Transfer Line Slave Device Operation SIO0 Data H L L L L L L L H H H H SIO0 FFH Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 ...

Page 375: ...n Transfer Line SIO0 Data H L L L L L L L H H H H SIO0 FFH SIO0 FFH Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave Device Operation Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 2 3 b Data ...

Page 376: ...Line SIO0 Address H L L L L H H H SIO0 FFH Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave Device Operation SIO0 FFH Figure 17 22 Data Transmission from Master to Slave Both Master and Slave Selected 9 Clock Wait 3 3 c Stop Condition ...

Page 377: ... Line SIO0 FFH H L L L L L L L H H Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave Device Operation SIO0 Data Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 1 3 a Start Condition to Address ...

Page 378: ...ansfer Line SIO0 FFH H L L L L L L L L L L H H Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave Device Operation SIO0 Data SIO0 Data Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 2 3 b Data ...

Page 379: ...Line SIO0 Address H L L L L L L H H Write SIO0 COI ACKD CMDD RELD CLD P27 SCL SDA0 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 Write SIO0 COI ACKD CMDD RELD CLD P27 WUP BSYE ACKE CMDT RELT CLC WREL SIC INTCSI0 CSIE0 P25 PM25 PM27 Slave Device Operation SIO0 Data Figure 17 23 Data Transmission from Slave to Master Both Master and Slave Selected 9 Clock Wait 3 3 c Stop Condition ...

Page 380: ...ut a start condition signal To set pin SCL to high level set bit 3 CLC of the interrupt timing specification register SINT to 1 After setting CLC clear CLC to 0 and return the SCL pin to low If CLC remains 1 no serial clock is output To output the start condition or stop condition from the master set CLC to 1 then make sure that bit 6 CLD of SINT is 1 This procedure must be followed because there ...

Page 381: ...ial I O shift register 0 SIO0 write instruction If the slave sends data the wait is immediately released by execution of an SIO0 write instruction and the clock rises without the start transmission bit being output in the data line Therefore as shown in Figure 17 25 data should be transmitted by manipulating the P27 output latch through the program At this time control the low level width a in Fig...

Page 382: ...e interrupt timing specify register SINT is set or when an instruction that writes data to the serial I O shift register 0 SIO0 is executed When the slave receives data the first bit of the data sent from the master may not be received if the SCL line immediately goes into a high impedance state after an instruction that writes data to SIO has been executed This is because SIO0 does not start oper...

Page 383: ...ommunication data Note The serial transfer status is the status since data has been written to the serial I O shift register 0 SIO0 until the interrupt request flag CSIIF0 is set to 1 by completion of the serial transfer Preventive measure The above phenomenon can be avoided by modifying the program Before executing the wake up function execute the following program that clears the serial transfer...

Page 384: ...CL pin in the input mode to protect the SCL line from adverse influ ence when the port mode is set by instruction 4 The P27 pin is set in the input mode when instruction 3 is executed 4 This instruction changes the mode from I2C bus mode to port mode 5 This instruction restores the I2C bus mode from the port mode 6 This instruction prevents the SDA0 pin from outputting a low level when instruction...

Page 385: ...utput latch by executing the bit manipulation instruction Figure 17 27 SCK0 SCL P27 Pin Configuration 2 In I2C bus mode The output level of the SCK0 SCL P27 pin is manipulated by bit 3 CLC of the interrupt timing specify register SINT 1 Set the serial operating mode register 0 CSIM0 SCL pin is set in the output mode and serial opera tion is enabled Set 1 to the P27 output latch SCL 0 while serial ...

Page 386: ...anipulation instruction Wait request signal Serial clock low while transfer is stopped SCL Figure 17 29 Logic Circuit of SCL Signal Remarks 1 This figure indicates the relation of the signals and does not indicate the internal circuit 2 CLC Bit 3 of interrupt timing specify register SINT ...

Page 387: ...the start bit of 8 bit data to undergo serial transfer is switchable between MSB and LSB connection is enabled with either start bit device The 3 wire serial I O mode is valid for connection of peripheral I O units and display controllers which incorporate a conventional synchronous serial interface such as the 75X XL 78K and 17K Series 3 3 wire serial I O mode with automatic transmit receive func...

Page 388: ... O shift register 1 SIO1 Automatic data transmit receive address pointer ADTP Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Control register Automatic data transmit receive control register ADTC Automatic data transmit receive interval specify register ADTI Port mode register 2 PM2 Note Note See Figure 6 5 and Figure 6 7 P20 P21 P23 to P26 Block Diagram and Figure 6 6 a...

Page 389: ...Register 1 SIO1 Hand shake Serial Clock Counter Selector Selector SO1 P21 PM21 P21 Output Latch DIR DIR Buffer RAM Automatic Data Transmit Receive Address Pointer ADTP SCK1 P22 PM22 Internal Bus TRF P22 Output Latch Match ADTI0 to ADTI4 Selector TO2 INTCSI1 Clear SIOI write Q R S Selector TCL 37 TCL 36 TCL 35 TCL 34 4 Timer Clock Select Register 3 fxx 2 to fxx 28 Internal Bus ARLD CSIE1 DIR ATE CS...

Page 390: ...RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated 2 Automatic data transmit receive address pointer ADTP This register stores value of the number of transmit data bytes 1 while the automatic transmit receive function is activated As data is transferred received it is automatically decremented ADTP is set with an 8 bit memo...

Page 391: ...r 1 CSIM1 Automatic data transmit receive control register ADTC Automatic data transmit receive interval specify register ADTI 1 Timer clock select register 3 TCL3 This register sets the serial clock of serial interface channel 1 TCL3 is set with an 8 bit memory manipulation instruction RESET input sets TCL3 to 88H Remark Besides setting the serial clock of serial interface channel 1 TCL3 sets the...

Page 392: ...313 kHz fX 25 156 kHz fX 26 78 1 kHz fX 27 39 1 kHz fX 28 19 5 kHz fX 29 9 8 kHz Other than above Setting prohibited 6 5 4 3 2 1 0 7 Symbol TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30 FF43H 88H R W Address After Reset R W MCS 1 MCS 0 Figure 18 2 Timer Clock Select Register 3 Format Caution When rewriting other data to TCL3 stop the serial transfer operation beforehand Remarks 1 fXX Main s...

Page 393: ...nable 6 5 4 3 2 1 0 7 Symbol CSIM1 CSIE1 DIR ATE 0 0 0 CSIM11 CSIM10 CSIM11 0 1 Serial Interface Channel 1 Clock Selection Clock externally input to SCK1 pinNote 1 8 bit timer register 2 TM2 output SCK1 Input 1 Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 CSIE1 0 CSIM10 0 1 FF68H 00H R W Address After Reset R W CSIM11 P20 PM21 P21 PM22 Note 3 Shift Register 1 Operation Se...

Page 394: ...ansmission reception This bit is set to 0 upon suspension of automatic transmission reception or when ARLD 0 During automatic transmission reception This bit is set to 1 when data is written to SIO1 R W R W R R ERR 0 1 Error Detection of Automatic Transmit Receive Function No error This bit is set to 0 when data is written to SIO1 Error occurred R W ARLD 0 1 Operating Mode Selection of Automatic T...

Page 395: ... 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ 4 Automatic data transmit receive interval specify register ADTI This register sets the automatic data transmit receive function data transfer interval ADTI is set by a 1 bit or 8 bit memory manipulation instruction RESET input sets ADTI to 00H Figure 18 5 Automatic Data Transmit Receive Interval Specify...

Page 396: ...bol ADTI ADTI7 0 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH 00H R W Address After Reset R W ADTI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 2 4 Note The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following exp...

Page 397: ...TI7 0 Data Transfer Interval Control No control of interval by ADTINote 1 Control of interval by ADTI ADTI0 to ADTI4 1 ADTI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 3 4 Notes 1 The interval is dependent only on CPU processing 2 The data transfer interval includes an ...

Page 398: ...bol ADTI ADTI7 0 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH 00H R W Address After Reset R W ADTI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ Figure 18 5 Automatic Data Transmit Receive Interval Specify Register Format 4 4 Note The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following exp...

Page 399: ...ire serial I O mode 3 wire serial I O mode with automatic transmit receive function 18 4 1 Operation stop mode Serial transfer is not carried out in the operation stop mode Thus power consumption can be reduced The serial I O shift register 1 SIO1 does not carry out shift operation either and thus it can be used as an ordinary 8 bit register In the operation stop mode the P20 SI1 P21 SO1 P22 SCK1 ...

Page 400: ...with the serial operating mode register 1 CSIM1 CSIM1 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM1 to 00H Notes 1 If the external clock input has been selected with CSIM11 set to 0 set bit 1 BUSY1 and bit 2 STRB of the automatic data transmit receive control register ADTC to 0 0 2 Can be used freely as port function 3 Can be used as P20 CMOS input output when...

Page 401: ...t transfer the SIO1 operation stops automatically and the interrupt request flag CSIIF1 is set Figure 18 6 3 Wire Serial I O Mode Timings Caution SO1 pin becomes low level by SIO1 write 3 MSB LSB switching as the start bit The 3 wire serial I O mode enables to select transfer to start from MSB or LSB Figure 18 7 shows the configuration of the serial I O shift register 1 SIO1 and internal bus As sh...

Page 402: ...e following two conditions are satisfied Serial interface channel 1 operation control bit CSIE1 1 Internal serial clock is stopped or SCK1 is a high level after 8 bit serial transfer Caution If CSIE1 is set to 1 after data write to SIO1 transfer does not start Upon termination of 8 bit transfer serial transfer automatically stops and the interrupt request flag CSIIF1 is set Figure 18 7 Circuit of ...

Page 403: ...bytes Handshake signals STB and BUSY are supported by hardware to transmit receive data continuously OSD On Screen Display LSI and peripheral LSI including LCD controller driver can be connected without difficulty 1 Register setting The 3 wire serial I O mode with automatic transmit receive function is set with the serial operating mode register 1 CSIM1 automatic data transmit receive control regi...

Page 404: ...timer register 2 TM2 output SCK1 Input 1 Clock specified with bits 4 to 7 of timer clock select register 3 TCL3 CSIE1 0 CSIM10 0 1 FF68H 00H R W Address After Reset R W CSIM11 P20 PM21 P21 PM22 Note 3 Shift Register 1 Operation Serial Clock Counter Operation Control SI1 P20 Pin Function SCK1 P22 Pin Function 1 0 1 0 0 0 1 1 Note 2 Note 2 Note 2 Note 2 Count operation SI1 Input Operation stop Clear...

Page 405: ...t to 0 when data is written to SIO1 Error occurred R W ARLD 0 1 Operating Mode Selection of Automatic Transmit Receive Function Single operating mode Repetitive operating mode R W RE 0 1 Receive Control of Automatic Transmit Receive Function Receive disable Receive enable R W ERCE 0 Error Check Control of Automatic Transmit Receive Function Error check disable Error check enable only when BUSY1 1 ...

Page 406: ...ystem clock oscillation frequency 3 fSCK Serial clock frequency fXX 26 fXX fSCK 28 0 5 fXX fSCK 36 1 5 fXX 26 Data Transfer Interval Specification fXX 5 0 MHz Operation ADTI4 ADTI3 ADTI2 ADTI1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MinimumNote 2 18 4 s 0 5 fSCK 31 2 s 0 5 fSCK 44 0 s 0 5 fSCK 56 8 s 0 5 fSCK 6...

Page 407: ...SCK 416 8 s 1 5 fSCK 6 5 4 3 2 1 0 7 Symbol ADTI ADTI7 0 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH 00H R W Address After Reset R W ADTI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ Note The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTI0 to ADTI4 Ho...

Page 408: ... FF6BH 00H R W Address After Reset R W ADTI7 0 Data Transfer Interval Control No control of interval by ADTINote 1 Control of interval by ADTI ADTI0 to ADTI4 1 ADTI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ Notes 1 The interval is dependent only on CPU processing 2 The data transfer interval includes an error The data transfer minimum and maxi...

Page 409: ...SCK 833 6 s 1 5 fSCK 6 5 4 3 2 1 0 7 Symbol ADTI ADTI7 0 0 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0 FF6BH 00H R W Address After Reset R W ADTI0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ Note The data transfer interval includes an error The data transfer minimum and maximum intervals are found from the following expressions n Value set in ADTI0 to ADTI4 Ho...

Page 410: ...e automatic data transmit receive interval specify register ADTI 4 Write any value to the serial I O shift register 1 SIO1 transfer start trigger Caution Writing any value to SIO1 orders the start of automatic transmit receive operation and the written value has no meaning The following operations are automatically carried out when a and b are set After the internal buffer RAM data specified with ...

Page 411: ...cuted the P23 STB and P24 BUSY pins can be used as normal input output ports Figure 18 8 shows the basic transmission reception mode operation timings and Figure 18 9 shows the operation flowchart Figure 18 10 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted or received Figure 18 8 Basic Transmission Reception Mode Operation Timings Cautions 1 Because in the basi...

Page 412: ...DTC Start Write transmit data in internal buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from internal buffer RAM to SIO1 Transmission reception operation Write receive data from SIO1 to internal buffer RAM Pointer ...

Page 413: ...ission reception point See Figure 18 10 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the internal buffer RAM to SIO1 When transmission of the fourth byte is completed the receive data 4 R4 is transferred from SIO1 to the internal buffer RAM and ADTP is decremented iii Completion of transmission reception See Figure 18 10 c When transmission of ...

Page 414: ...O1 1 CSIIF1 0 ADTP Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H Receive data 4 R4 SIO1 0 CSIIF1 2 ADTP 1 Figure 18 10 Internal Buffer RAM Operation in 6 Byte Transmission Reception in Basic Transmit Receive Mode 2 2 b 4th byte transmission reception c Completion of transmission reception ...

Page 415: ...ode operation timings and Figure 18 12 shows the operation flowchart Figure 18 13 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted or received Figure 18 11 Basic Transmission Mode Operation Timings SCK1 SO1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CSIIF1 TRF Interval Cautions 1 Because in the basic transmission mode the automatic transmit receive function ...

Page 416: ...receive control register ADTC Start Write transmit data in internal buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from internal buffer RAM to SIO1 Transmission operation Pointer value 0 No TRF 0 No End Yes Yes Decr...

Page 417: ...o SIO1 When transmission of the first byte is completed automatic data transmit receive address pointer ADTP is decremented Then transmit data 2 T2 is transferred from the internal buffer RAM to SIO1 ii 4th byte transmission point See Figure 18 13 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from the internal buffer RAM to SIO1 When transmission of the fourth...

Page 418: ... 6 T6 FADFH FAC5H FAC0H SIO1 1 CSIIF1 0 ADTP Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 2 ADTP 1 Figure 18 13 Internal Buffer RAM Operation in 6 Byte Transmission in Basic Transmit Mode 2 2 b 4th byte transmission point c Completion of transmission ...

Page 419: ... P23 STB and P24 BUSY pins can be used as ordinary input output ports The repeat transmission mode operation timing is shown in Figure 18 14 and the operation flowchart in Figure 18 15 Figure 18 16 shows the operation of the internal buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode Figure 18 14 Repeat Transmission Mode Operation Timing D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D...

Page 420: ...egister 1 Start Write transmit data in internal buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission reception operation interval time in ADTI Write any data to SIO1 Start trigger Write transmit data from internal buffer RAM to SIO1 Transmission operation Pointer value 0 No Yes Decrement pointer value Software Executio...

Page 421: ...to SIO1 ii Upon completion of transmission of 6 bytes See Figure 18 16 b Even when sending of the 6th byte is completed the interrupt request flag CSIIF1 is not set The initial pointer value is reset in ADTP iii 7th byte transmission point See Figure 18 16 c Transmit data 1 T1 is transferred from the internal buffer RAM to SIO1 again When transmission of the first byte is completed ADTP is decreme...

Page 422: ...DFH FAC5H FAC0H SIO1 0 CSIIF1 5 ADTP 1 Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FADFH FAC5H FAC0H SIO1 0 CSIIF1 0 ADTP Figure 18 16 Internal Buffer RAM Operation in 6 Byte Transmission in Repeat Transmit Mode 2 2 b Upon completion of transmission of 6 bytes c 7th byte transmission point ...

Page 423: ...C is set to 0 after transfer of the 8th bit and all the port pins used with the serial interface pins for dual function P20 SI1 P21 SO1 P22 SCK1 P23 STB and P24 BUSY are set to the port mode To restart auto send and receive set CSIE1 at 1 and write the desired value in serial I O shift register 1 SIO1 The remaining can be transmitted in this way Cautions 1 If the HALT instruction is executed durin...

Page 424: ...t 1 The system configuration between the master device and slave device in cases where the busy control option is used is shown in Figure 18 18 Figure 18 18 System Configuration When the Busy Control Option Is Used The master device inputs the busy signal output by the slave device to pin BUSY P24 In sync with the fall of the serial clock the master device samples the input busy signal Even if the...

Page 425: ...busy signal becomes inactive the wait is canceled If the sampled busy signal is inactive sending or receiving of the next 8 bit data begins from the fall of the next serial clock cycle Furthermore the busy signal is asynchronous with the serial clock so even if the slave side inactivates the busy signal it takes nearly 1 clock cycle at the most until it is sampled again Also it takes another 0 5 c...

Page 426: ...al operation mode register 1 CSIM1 at 1 Set bit 2 STRB of the auto data send and receive control register ADTC at 1 Normally busy control and strobe control are used simultaneously as handshake signals In this case together with output of the strobe signal from pin STB P23 pin BUSY P24 can be sampled and sending or receiving can wait while the busy signal is being input If strobe control is not ca...

Page 427: ...4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TRF Busy Input Valid Busy Input Release CSIIF1 Figure 18 21 Operation Timings When Using Busy Strobe Control Option BUSY0 0 Caution When TRF is cleared the SO1 pin becomes low level Remarks CSIIF1 Interrupt request flag TRF Bit 3 of the auto data send and receive control register ADTC ...

Page 428: ...thin 2 clock cycles The master device side samples the busy signal in sync with the fall of the serial clock s front side If no bit slippage is occurring the busy signal will be inactive in sampling for 8 clock cycles If the busy signal is found to be active in sampling it is regarded as an occurrence of bit slippage error processing is executed bit 4 ERR of the auto data send and receive control ...

Page 429: ... transmit receive interval specification register ADTI and the CPU processing at the rising edge of the eighth serial clock Whether it depends on the ADTI or not can be selected by the setting of its bit 7 ADTI7 When it is set to 0 the interval depends only on the CPU processing When it is set to 1 the interval depends on the contents of the ADTI or CPU processing whichever is greater When the aut...

Page 430: ...rmat for the intervals which are set by the ADTI Table 18 2 Interval Timing Through CPU Processing When the Internal Clock Is Operating CPU Processing Interval Time When using multiplication instruction Max 2 5TSCK 13TCPU When using division instruction Max 2 5TSCK 20TCPU External access 1 wait mode Max 2 5TSCK 9TCPU Other than above Max 2 5TSCK 7TCPU TSCK 1 fSCK fSCK Serial clock frequency TCPU 1...

Page 431: ...t be selected so that the interval may be longer than the values shown as follows Table 18 3 Interval Timing Through CPU Processing When the External Clock Is Operating CPU Processing Interval Time When using multiplication instruction 13TCPU When using division instruction 20TCPU External access 1 wait mode 9TCPU Other than above 7TCPU TCPU 1 fCPU fCPU CPU clock set by the bits 0 to 2 PCC0 to PCC...

Page 432: ...432 MEMO ...

Page 433: ...g the dedicated UART baud rate generator 3 3 wire serial I O mode MSB first LSB first switchable In this mode 8 bit data transfer is performed using three lines the serial clock SCK2 and serial data lines SI2 SO2 In the 3 wire serial I O mode simultaneous transmission and reception is possible increasing the data transfer processing speed Either the MSB or LSB can be specified as the start bit for...

Page 434: ...figuration Register Transmit shift register TXS Receive shift register RXS Receive buffer register RXB Control register Serial operating mode register 2 CSIM2 Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC Port Mode Register 7 PM7 Note Note See Figure 6 15 P70 Block Diagram and Figure 6 16 P71 and P72 Bl...

Page 435: ... 22 CSCK INTSER SCK Output Control Circuit Baud Rate Generator fxx to fxx 210 Internal Bus INTST SCK Baud Rate Generator Control Register Note Serial Operating Mode Register 2 PE FE OVE Transmission Control Circuit PM71 ISRM ASCK SCK2 P72 PM72 Direction Control Circuit Transmit Shift Register TXS SIO2 RXE PS1 PS0 CL SL ISRM TXE SCK 4 4 CSIE2 TXE RXE MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0 Figure 1...

Page 436: ...Control Register 4 TXE CSIE2 5 Bit Counter Selector Selector Decoder 1 2 Selector Transmit Clock 1 2 Selector Receive Clock Match Match MDL0 to MDL3 5 Bit Counter RXE Start Bit Detection Selector fxx to fxx 210 TPS0 to TPS3 SCK ASCK SCK2 P72 4 4 Start Bit Sampling Clock Figure 19 2 Baud Rate Generator Block Diagram ...

Page 437: ...time one byte of data is received new receive data is transferred from the receive shift register RXS If the data length is specified as 7 bits the receive data is transferred to bits 0 to 6 of RXB and the MSB of RXB is always set to 0 RXB is read with an 8 bit memory manipulation instruction It cannot be written to RXB value is FFH after RESET input Caution RXB and the transmit shift register TXS...

Page 438: ... 2 is controlled by the following four registers Serial operating mode register 2 CSIM2 Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS Baud rate generator control register BRGC 1 Serial operating mode register 2 CSIM2 This register is set when serial interface channel 2 is used in the 3 wire serial I O mode CSIM2 is set with a 1 bit or 8 bit mem...

Page 439: ...ion enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled PS1 0 1 0 1 bit 1 2 bits 0 Parity Bit Specification No Parity Even parity PS0 0 1 0 parity always added in transmission No parity test in reception parity error not generated 0 1 1 Odd parity 0 Note When SCK is set to 1 and the baud rate generator output is selected the ASCK pin can be used as an i...

Page 440: ...an above Setting prohibited P72 SCK2 ASCK Pin Functions P71 SO2 TxD Pin Functions P70 SI2 RxD Pin Functions Shift Clock Start Bit TXE RXE SCK CSIE2 CSIM22 CSCK PM70 P70 PM71 P71 PM72 P72 ASIM CSIM2 0 0 0 1 1 0 1 1 1 1 Note 2 Note 2 0 1 0 1 MSB LSB Internal clock SI2 SI2 SO2 CMOS output SCK2 output Other than above Setting prohibited Note 2 Note 2 SO2 CMOS output P72 SCK2 ASCK Pin Functions P71 SO2...

Page 441: ... Notes 1 The receive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be generated until RXB is read 2 Even if the stop bit length has been set as 2 bits by bit 2 SL of the asynchronous serial interface mode register ASIM only single stop bit detection is performed during reception 3 Asynchronous serial interface status register ASIS This is a reg...

Page 442: ... fSCK 30 fSCKNote 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k 4 Baud rate generator control register BRGC This register sets the serial clock for serial interface channel 2 BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H Figure 19 6 Baud Rate Generator Control R...

Page 443: ... fXX 26 fX 26 78 1 kHz fX 27 39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution If data is written to BRGC during the communication operation the baud rate generator output is disrupted and communication cannot be performed normally Therefore do not write ...

Page 444: ...DL0 to MDL3 0 k 14 Table 19 3 Relationship Between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 75 00H 1 73 0BH 1 14 EBH 1 14 110 06H 0 88 E6H 0 88 03H 2 01 E3H 2 01 150 00H 1 73 E0H 1 73 EBH 1 14 DBH 1 14 300 E0H 1 73 D0H 1 73 DBH 1 14 CBH 1 14 600 D0H 1 73 C0H 1 73 CBH 1 14 BBH 1...

Page 445: ...rom the ASCK pin is obtained with the following expression Baud rate Hz fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 19 4 Relationship Between ASCK Pin Input Frequency and Baud Rate When BRGC Is Set to 00H Baud Rate bps ASCK Pin Input Frequency 75 2 4 kHz 110 3 52 kHz 150 4 8 kHz 300 9 6 kHz 600 19 2 kHz 1200 38 4 kHz 2400 76 8 kHz 4800 153 6 kHz 9600 307 2 k...

Page 446: ...D P71 SO2 TxD and P72 SCK2 ASCK pins can be used as normal input output ports 1 Register setting The operation stop mode is set by the serial operating mode register 2 CSIM2 and asynchronous serial interface mode register ASIM a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H CSIM 22 6 5 4 3 2 1 0 7 Symbol CSIM...

Page 447: ...Reset R W RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled b Asynchronous serial interface mode register ASIM ASIM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIM to 00H ...

Page 448: ...ator is incorporated allowing communication over a wide range of baud rates In addition the baud rate can be defined by scaling the input clock to the ASCK pin The MIDI standard baud rate 31 25 kbps can be used by employing the dedicated UART baud rate generator 1 Register setting The UART mode is set by the serial operating mode register 2 CSIM2 asynchronous serial interface mode register ASIM as...

Page 449: ...Character Length Specification 7 bits 8 bits RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled PS1 0 1 0 1 bit 1 2 bits 0 Parity Bit Specification No Parity Even parity PS0 0 1 0 parity always added in transmission No parity test in reception parity error not generated 0 1 1...

Page 450: ...is not detected PE 0 1 Parity Error Flag Parity error not generated Parity error generated When transmit data parity does not match c Asynchronous serial interface status register ASIS ASIS is set with 8 bit memory manipulation instruction RESET input sets ASIS to 00H Notes 1 The receive buffer register RXB must be read when an overrun error is generated Overrun errors will continue to be generate...

Page 451: ...8 fSCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k d Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H fSCK 5 bit counter source cl...

Page 452: ...9 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Caution If data is written to BRGC during a communication operation the baud rate generator output is disrupted and communication cannot be performed normally Therefore do not write data to BRGC during a communicat...

Page 453: ...DL0 to MDL3 0 k 14 Table 19 5 Relationship Between Main System Clock and Baud Rate fx 5 0 MHz fx 4 19 MHz MCS 1 MCS 0 MCS 1 MCS 0 BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error BRGC Set Value Error 75 00H 1 73 0BH 1 14 EBH 1 14 110 06H 0 88 E6H 0 88 03H 2 01 E3H 2 01 150 00H 1 73 E0H 1 73 EBH 1 14 DBH 1 14 300 E0H 1 73 D0H 1 73 DBH 1 14 CBH 1 14 600 D0H 1 73 C0H 1 73 CBH 1 14 BBH 1...

Page 454: ...rom the ASCK pin is obtained with the following expression Baud rate Hz fASCK Frequency of clock input to ASCK pin k Value set in MDL0 to MDL3 0 k 14 Table 19 6 Relationship Between ASCK Pin Input Frequency and Baud Rate When BRGC Is Set to 00H Baud Rate bps ASCK Pin Input Frequency 75 2 4 kHz 110 3 52 kHz 150 4 8 kHz 300 9 6 kHz 600 19 2 kHz 1200 38 4 kHz 2400 76 8 kHz 4800 153 6 kHz 9600 307 2 k...

Page 455: ... for each data frame is specified with the asynchronous serial interface mode register ASIM When 7 bits are selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most significant bit bit 7 is always 0 The serial transmission rate is set by ASIM and the baud rate generator control register ...

Page 456: ...ata is counted If it is odd a parity error occurs ii Odd parity Transmission Conversely to the situation with even parity the number of bits with a value of 1 including the parity bit in the transmit data is controlled to be odd The value of the parity bit is as follows Number of bits with a value of 1 in transmit data is odd 0 Number of bits with a value of 1 in transmit data is even 1 Reception ...

Page 457: ...sion completion interrupt request INTST is generated Figure 19 8 Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing a Stop bit length 1 b Stop bit length 2 Caution Rewriting of the asynchronous serial interface mode register ASIM should not be performed during a transmit operation If rewriting of the ASIM register is performed during transmission subsequent t...

Page 458: ...ception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to the receive buffer register RXB and a reception completion interrupt request INTSR is generated Even if an error occurs the receive data for which the error occurred is transferred to RXB When an error occurs if bit 1 ISRM of ASIM is cleared 0 INTSR is generated If IS...

Page 459: ...y error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive register buffer Figure 19 10 Receive Error Timing Note If a receive error is generated while bit 1 ISRM of the asynchronous serial interface mode register ASIM is set to 1 INTSR is not generated ...

Page 460: ...e receive buffer register RXB and whether or not a receive completion interrupt INTSR is generated differ depending on the timing The timing is shown in Figure 19 11 Figure 19 11 Receive Buffer Register RXB Status and Receive Completion Interrupt Request INTSR Generation When Receiving Is Terminated Parity RxD Pin RXB INTSR 3 1 2 When RXE is set to 0 at a time indicated by 1 RXB holds the previous...

Page 461: ...The 3 wire serial I O mode is set with the serial operating mode register 2 CSIM2 and serial bus interface control register SBIC a Serial operating mode register 2 CSIM2 CSIM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIM2 to 00H Caution Ensure that bits 0 and 3 to 6 are set to 0 6 5 4 3 2 1 0 7 Symbol CSIM2 CSIE2 0 0 0 0 CSIM 22 CSCK 0 CSCK 0 1 Serial Operatin...

Page 462: ... of error generation SL Transmit Data Stop Bit Length Specification CL 1 Character Length Specification 7 bits 8 bits RXE 0 1 Receive Operation Control Receive operation stopped Receive operation enabled TXE 0 1 Transmit Operation Control Transmit operation stopped Transmit operation enabled PS1 0 1 0 1 bit 1 2 bits 0 Parity Bit Specification No Parity Even parity PS0 0 1 0 parity always added in ...

Page 463: ...18 fSCK 19 fSCK 20 fSCK 21 fSCK 22 fSCK 23 fSCK 24 fSCK 25 fSCK 26 fSCK 27 fSCK 28 fSCK 29 fSCK 30 fSCK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 5 4 3 2 1 0 7 Symbol BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R W Address After Reset R W k continued c Baud rate generator control register BRGC BRGC is set with an 8 bit memory manipulation instruction RESET input sets BRGC to 00H fSCK 5 bit c...

Page 464: ... 39 1 kHz 7 1 1 0 0 fXX 27 fX 27 39 1 kHz fX 28 19 5 kHz 8 1 1 0 1 fXX 28 fX 28 19 5 kHz fX 29 9 8 kHz 9 1 1 1 0 fXX 29 fX 29 9 8 kHz fX 210 4 9 kHz 10 Other than above Setting prohibited Note If data is written to BRGC during a communication operation the baud rate generator output is disrupted and communication cannot be performed normally Therefore do not write data to BRGC during a communicati...

Page 465: ...to set MDL0 to MDL3 to 1 1 1 1 The serial clock frequency is 1 2 the source clock frequency of the 5 bit counter ii When the baud rate generator is used Select a serial clock frequency with TPS0 to TPS3 Be sure then to set MDL0 to MDL3 to 1 1 1 1 The serial clock frequency is calculated by the following formula Serial clock frequency Hz Remarks 1 fX Main system clock oscillation frequency 2 fXX Ma...

Page 466: ... in synchronization with the serial clock Transmit shift register TXS SIO2 and receive shift register RXS shift operations are performed in synchronization with the fall of the serial clock SCK2 Then transmit data is held in the SO2 latch and output from the SO2 pin Also receive data input to the SI2 pin is latched in the receive buffer register RXB SIO2 on the rise of SCK2 At the end of an 8 bit ...

Page 467: ...he SIO2 shift order remains unchanged Thus switching between MSB first and LSB first must be performed before writing data to the shift register 4 Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS SIO2 when the following two conditions are satisfied Serial interface channel 2 operation control bit CSIE2 1 Internal serial clock is stopped or S...

Page 468: ...to be generated will be generated Figure 19 14 illustrates the operation above Figure 19 14 Receive Completion Interrupt Request Generation Timing When ISRM 1 Remark ISRM Bit 1 of asynchronous serial interface mode register ASIM fSCK 5 bit counter source clock of baud rate generator RXB Receive buffer register To avoid this phenomenon implement the following countermeasures Countermeasures In the ...

Page 469: ... rate selected with the baud rate generator control register BRGC 1 baud rate T2 The amount of time for 2 clocks of 5 bit counter source clock fSCK selected with BRGC Example of countermeasures An example of the countermeasures is shown below Condition fX 5 0 MHz Processor clock control register PCC 00H Oscillation mode selection register OSMS 01H Baud rate generator control register BRGC B0H when...

Page 470: ...EL 2 Example INTSER is Generated 7 Clocks MIN of CPU Clock Time from Interrupt Request to Servicing Instructions for 2205 clocks MIN of CPU clock are required UART Receive Error Interrupt INTSER Servicing EI RETI MOV A RXB Main Processing ...

Page 471: ... timer interrupt request or external interrupt request generation then output externally This is called the real time output function The pins that output data externally are called real time output ports By using a real time output a signal that has no jitter can be output This port is therefore suitable for control of stepping motors etc Port mode real time output port mode can be specified bit ...

Page 472: ...ster Port mode register 12 PM12 Real time output port mode register RTPM Real time output port control register RTPC Figure 20 1 Real time Output Port Block Diagram Internal Bus Real time Output Port Control Register EXTR BYTE Output Trigger Control Circuit Real time Output Buffer Register Higher 4 Bits RTBH Real time Output Buffer Register Lower 4 Bits RTBL Output Latch P120 P127 Real time Output...

Page 473: ...2 Real time Output Buffer Register Configuration Table 20 2 Operation in Real time Output Buffer Register Manipulation During Read Note 1 During Write Note 2 Higher 4 Bits Lower 4 Bits Higher 4 Bits Lower 4 Bits RTBL RTBH RTBL Invalid RTBL RTBH RTBH RTBL RTBH Invalid RTBL RTBH RTBL RTBH RTBL RTBH RTBH RTBL RTBH RTBL Notes 1 Only the bits set in the real time output port mode can be read When a bit...

Page 474: ...port mode bit wise RTPM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Figure 20 4 Real time Output Port Mode Register Format Cautions 1 When using these bits as a real time output port set the ports to which real time output is performed to the output mode clear the corresponding bit of the port mode register 12 PM12 to 0 2 In the port specified...

Page 475: ...igure 20 5 Real time Output Port Control Register Format Table 20 3 Real time Output Port Operating Mode and Output Trigger BYTE EXTR Operating Mode RTBH Port Output RTBL Port Output 0 INTTM2 INTTM1 1 INTTM1 INTP2 0 INTTM1 1 INTP2 7 0 Symbol RTPC 6 0 5 0 4 0 3 0 2 0 1 BYTE 0 EXTR Address FF36H 00H After Reset R W R W EXTR 0 1 Real time Output Control by INTP2 INTP2 not specified as real time outpu...

Page 476: ...476 MEMO ...

Page 477: ...kable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register PR0L PR0H PR1L Multiple high priority interrupts can be applied to low priority interrupts If two or more interrupts with the same priority are simultaneously generated each interrupts has a predetermined priority see Table 21 1 A standby release sig...

Page 478: ...TP5 0010H 7 INTP6 0012H 8 INTCSI0 End of serial interface channel 0 transfer Internal 0014H B 9 INTCSI1 End of serial interface channel 1 transfer 0016H Serial interface channel 2 UART reception 0018H error generation End of serial interface channel 2 001AH UART reception End of serial interface channel 2 3 wired transfer INTST End of serial interface channel 2 001CH UART transfer 10 INTSER 11 INT...

Page 479: ...eration of 8 bit timer event 0024H counter 1 match signal INTTM2 Generation of 8 bit timer event 0026H counter 2 match signal 18 INTAD End of A D converter conversion 0028H Software BRK BRK instruction execution 003EH E Interrupt Type Default Priority Internal External Vector Table Address Basic Configuration Type Note 1 Note 2 14 17 13 Notes 1 Default priorities are intended for two or more simul...

Page 480: ...S External Interrupt Mode Register INTM0 Internal Bus IE PR ISP MK IF Interrupt Request Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Priority Control Circuit Vector Table Address Generator Standby Release Signal Interrupt Request Figure 21 1 Basic Configuration of Interrupt Function 1 2 A Internal non maskable interrupt B Internal maskable interrupt C...

Page 481: ...ctor Interrupt Request IE PR ISP MK IF Priority Control Circuit Vector Table Address Generator Standby Release Signal Internal Bus Figure 21 1 Basic Configuration of Interrupt Function 2 2 D External maskable interrupt except INTP0 E Software interrupt Remark IF Interrupt request flag IE Interrupt enable flag ISP Inservice priority flag MK Interrupt mask flag PR Priority specify flag ...

Page 482: ...g to interrupt request sources Table 21 2 Various Flags Corresponding to Interrupt Request Sources Interrupt Source Interrupt Request Flag Interrupt Mask Flag Priority Order Specification Flag Register Register Register INTWDT TMIF4 IF0L TMMK4 MK0L TMPR4 PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 INTP3 PIF3 PMK3 PPR3 INTP4 PIF4 PMK4 PPR4 INTP5 PIF5 PMK5 PPR5 INTP6 PIF6 PMK...

Page 483: ...hen a watchdog timer is used as an interval timer If a watchdog timer is used in watchdog timer mode 1 set TMIF4 flag to 0 2 Set always 0 in IF1L bits 3 to 6 1 Interrupt request flag registers IF0L IF0H IF1L The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed It is cleared to 0 when an instruction is executed upon acknowledgmen...

Page 484: ...value becomes undefined 2 Because port 0 has an alternate function as the external interrupt request input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 3 Set always 1 in MK1L bits 3 to 6 2 Interrupt mask flag registers MK0L MK0H MK1L The interrup...

Page 485: ...FFH R W PR Cautions 1 If a watchdog timer is used in watchdog timer mode 1 set TMPR4 flag to 1 2 Set always 1 in PR1L bits 3 to 7 3 Priority specify flag registers PR0L PR0H and PR1L The priority specify flag is used to set the corresponding maskable interrupt priority orders PR0L PR0H and PR1L are set with a 1 bit or 8 bit memory manipulation instruction If PR0L and PR0H are used as a 16 bit regi...

Page 486: ... ES20 0 0 1 1 INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES31 0 1 0 1 ES30 4 External interrupt mode register INTM0 INTM1 These registers set the valid edge for INTP0 to INTP6 INTM0 and INTM1 are set by 8 bit memory manipulation instructions RESET input sets these registers to 00H Figure 21 5 External Interrupt Mode Register 0 Format Cautio...

Page 487: ...41 0 ES40 0 1 0 1 ES40 0 0 1 1 INTP4 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES51 0 1 0 1 ES50 0 0 1 1 INTP5 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES61 0 1 0 1 ES60 0 0 1 1 INTP6 Valid Edge Selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES71 0 1 0 1 E...

Page 488: ... in the HALT mode Remarks 1 N Value N 0 to 4 at bits 0 to 2 PCC0 to PCC2 of processor clock control register 2 fXX Main system clock frequency fX or fX 2 3 fX Main system clock oscillation frequency 4 MCS Bit 0 of oscillation mode selection register OSMS 5 Values in parentheses when operated with fX 5 0 MHz 5 Sampling clock select register SCS This register is used to set the valid edge clock samp...

Page 489: ... During Rising Edge Detection a When input is less than the sampling cycle tSMP c When input is twice or more than the cycle frequency tSMP tSMP Sampling Clock INTP0 PIF0 2 is the second time in succession that sampling has found the INTP0 level to be high so the PIF0 flag is set at 1 1 2 tSMP Sampling Clock INTP0 PIF0 At the point when the level of INTP0 is found to be high the second time in suc...

Page 490: ...aved to the stack and the IE flag is set at 0 Also when a maskable interrupt request is received the contents of the received interrupt priority order specification flag are transferred to the ISP flag The contents of the PSW are also saved to the stack by the PUSH PSW command The stack contents are recovered by the RETI RETB and POP PSW commands RESET input sets PSW to 02H Figure 21 9 Program Sta...

Page 491: ...erated during execution of a non maskable interrupt service program is received after the execution of the non maskable interrupt service program that is currently processing is completed after the RETI command is executed and 1 command of the main routine is executed If a new non maskable interrupt request is generated twice or more during non maskable interrupt service program execution only one...

Page 492: ...val timer Start No Yes Yes No Yes No Yes No Yes No Figure 21 10 Flowchart from the Time a Non maskable Interrupt Request Is Generated Until It Is Received WDTM Watchdog timer mode register WDT Watchdog timer Figure 21 11 Non Maskable Interrupt Request Acknowledge Timing TMIF4 Watchdog Timer Interrupt Request Flag Instruction Instruction CPU Processing TMIF4 PSW and PC Save Jump to Interrupt Servic...

Page 493: ...ted during non maskable interrupt servicing program execution Main Routine NMI Request 1 NMI Request 1 executed NMI Request 2 held 1 Instruction Execution Held NMI Request 2 processed NMI Request 2 NMI Request 3 is not received Even if more than 2 NMI requests are generated they can only be received 1 time Main Routine NMI Request 1 NMI Request 1 executed NMI Request 2 held NMI Request 3 held 1 In...

Page 494: ...clocks Note If an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request specified for higher priority with the priority specify flag is acknowledged first Also when the priority order specification flag specifies the same priority order for two inte...

Page 495: ...ceived or low priority order interrupt being processed Start IF 1 MK 0 PR 0 Any Simultaneously generated PR 0 interrupt requests Any Simultaneously generated high priority interrupt requests IE 1 ISP 1 Vectored interrupt servicing Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt request reserve Interrupt req...

Page 496: ...ng Maximum Time Remark 1 clock fCPU CPU clock fCPU 1 Instruction Divide Instruction PSW and PC Save Jump to Interrupt Servicing 6 Clocks Interrupt Servicing Program 33 Clocks 32 Clocks CPU Processing IF PR 1 IF PR 0 25 Clocks fCPU 1 Instruction Instruction PSW and PC Save Jump to Interrupt Servicing 6 Clocks Interrupt Servicing Program 8 Clocks 7 Clocks CPU Processing IF PR 1 IF PR 0 ...

Page 497: ...mand during interrupt processing and permit interrupt reception Also even if interrupt reception is permitted there are some cases where multiple interrupts are not permitted but that is controlled by the interrupts priority order There are two types of interrupt priority order the default priority order and the programmable priority order but control of multiple interrupts is controlled by progra...

Page 498: ...tiple interrupt disable 3 ISP and IE are the flags contained in PSW ISP 0 An interrupt with higher priority is being serviced ISP 1 An interrupt request is not accepted or an interrupt with lower priority is being serviced IE 0 Interrupt request acknowledge is disabled IE 1 Interrupt request acknowledge is enabled 4 PR is a flag contained in PR0L PR0H and PR1L PR 0 Higher priority level PR 1 Lower...

Page 499: ...issued and the interrupt request reception permitted status must exist Example 2 Example of multiple interrupts not being generated due to priority order control During processing of interrupt INTxx interrupt request INTyy was generated but the priority order of this interrupt was lower than that of INTxx so it was not received and multiple interrupts were not generated Interrupt request INTyy was...

Page 500: ...being generated because an interrupt was not permitted In processing of interrupt INTxx interrupt reception was not permitted the IE command was not issued so interrupt request INTyy was not received and multiple interrupts were not generated Interrupt request INTyy was held and received after 1 main processing command was executed PR 0 High Priority Order Level IE 0 Interrupt Request Reception Pr...

Page 501: ...0L PR0H PR1L INTM0 INTM1 registers Caution The BRK command is not an interrupt request hold command like those above However in a software interrupt that is started by execution of the BRK command the IE flag is cleared to 0 Therefore even if a maskable interrupt is generated during execution of the BRK command the interrupt request is not received However a non maskable interrupt request is accep...

Page 502: ...t Factors Name Trigger INTWT Watch timer overflow Internal INTPT4 Falling edge detection at port 4 External Figure 21 18 Basic Configuration of Test Function Remark IF test input flag MK test mask flag 21 5 1 Registers controlling the test function The test function is controlled by the following three registers Interrupt request flag register 1L IF1L Interrupt mask flag register 1L MK1L Key retur...

Page 503: ...ble at the time the standby mode is released by the watch timer It is set by a 1 bit memory manipulation instruction and 8 bit memory manipulation instruction It is set to FFH by the RESET signal input Figure 21 20 Format of Interrupt Mask Flag Register 1L Caution Be sure to set bits 3 through 6 to 1 7 WTMK Symbol MK1L 6 1 5 1 4 0 3 0 2 ADMK 1 TMMK2 0 TMMK1 Address FFE6H FFH After Reset R W R W 0 ...

Page 504: ...ear KRIF to 0 not cleared to 0 automatically 21 5 2 Test input signal acknowledge operation 1 Internal test signal INTWT When the clock timer overflows a internal test input signal INTWT is generated and this causes the WTIF flag to be set At this time a standby release signal is generated if not masked by an interrupt mask flag WTMK If the WTIF flag is checked for a shorter period than the clock ...

Page 505: ... P47 A8 to A15 Address bus P50 to P57 RD Read strobe signal P64 WR Write strobe signal P65 WAIT Wait signal P66 ASTB Address strobe signal P67 Table 22 2 State of Ports 4 to 6 Pins in External Memory Expansion Mode Ports and bits Port 4 Port 5 Port 6 0 to 7 0 1 2 3 4 5 6 7 0 to 3 4 to 7 Single chip mode Port Port Port Port 256 byte expansion mode Address data Port Port RD WR WAIT ASTB 4 Kbyte expa...

Page 506: ...56FY and of the µPD78P058F and 78P058FY when the internal PROM is 48 Kbytes FFFFH SFR Internal High Speed RAM FF00H FEFFH FB00H FAFFH FAE0H FADFH FAC0H FABFH FA80H FA7FH D000H CFFFH C100H C0FFH C000H BFFFH 0000H Reserved Internal Buffer RAM Reserved Full Address Mode when MM2 to MM0 111 or 16 Kbyte Expansion Mode when MM2 to MM0 101 4 Kbyte Expansion Mode when MM2 to MM0 100 Single chip Mode 256 b...

Page 507: ...dress Mode when MM2 to MM0 111 or 16 Kbyte Expansion Mode when MM2 to MM0 101 4 Kbyte Expansion Mode when MM2 to MM0 100 Single chip Mode 256 byte Expansion Mode when MM2 to MM0 011 Figure 22 1 Memory Map When Using External Device Expansion Function 2 2 b µPD78058F 78058FY 78P058F 78P058FY Memory c µPD78058F 78058FY 78P058F 78P058FY Memory map when internal ROM PROM size is 56 Kbytes map when int...

Page 508: ... No wait Wait one wait state insertion Setting prohibited Wait control by external wait pin 22 2 External Device Expansion Function Control Register The external device expansion function is controlled by the memory expansion mode register MM and memory size switching register IMS 1 Memory expansion mode register MM MM sets the wait count and external expansion area and also sets the input output ...

Page 509: ... to the value indicated in Table 22 3 Figure 22 3 Memory Size Switching Register Format Note The values after reset depend on the product See Table 22 3 Table 22 3 Values When the Memory Size Switching Register Is Reset Part Number Reset Value µPD78056F 78056FY CCH µPD78058F 78058FY CFH 1 1 48 Kbytes 56 Kbytes 1 1 0 1 0 0 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 Address FFF0...

Page 510: ... not output maintains high level 3 WAIT pin Alternate function P66 External wait signal input pin When the external wait is not used the WAIT pin can be used as an input output port During internal memory access the external wait signal is ignored 4 ASTB pin Alternate function P67 Address strobe signal output pin Timing signal is output without regard to the data accesses and instruction fetches f...

Page 511: ...IT ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Higher Address Internal Wait Signal 1 clock wait ASTB RD AD0 to AD7 A8 to A15 Lower Address Operation Code Higher Address Figure 22 4 Instruction Fetch from External Memory a No wait PW1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ...

Page 512: ...dress WAIT ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data Higher Address Internal Wait Signal 1 clock wait Higher Address ASTB RD AD0 to AD7 A8 to A15 Lower Address Read Data Figure 22 5 External Memory Read Timing a No wait PW1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ...

Page 513: ...te Data ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Higher Address Internal Wait Signal 1 clock wait Hi Z ASTB WR AD0 to AD7 A8 to A15 Lower Address Write Data Hi Z Higher Address Figure 22 6 External Memory Write Timing a No wait PW1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ...

Page 514: ... Address Higher Address Internal Wait Signal 1 clock wait Hi Z ASTB RD WR AD0 to AD7 A8 to A15 Write Data Read Data ASTB RD WR AD0 to AD7 A8 to A15 Lower Address Write Data Higher Address Hi Z Read Data Figure 22 7 External Memory Read Modify Write Timing a No wait PW1 PW0 0 0 setting b Wait PW1 PW0 0 1 setting c External wait PW1 PW0 1 1 setting ...

Page 515: ...onsumption Because this mode can be cleared upon interrupt request it enables intermittent operations to be carried out However because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared select the HALT mode if it is necessary to start processing immediately upon interrupt request In any mode all the contents of the register flag and data memory jus...

Page 516: ...ter the STOP mode is cleared a in the figure below This applies to STOP mode clearance by RESET input as well as STOP mode clearance by interrupt request generation Remarks 1 fXX Main system clock frequency fX or fX 2 2 fX Main system clock oscillation frequency 3 MCS Bit 0 of oscillation mode select register OSMS 4 Values in parentheses apply to operating at fX 5 0 MHz Address FFFAH 04H After Res...

Page 517: ...rable when watch timer output is selected as count clock fXT is selected as count clock of watch timer or when TI00 is selected 8 bit timer event counter Operable Operable when TI1 or TI2 is selected as count clock Watch timer Operable when fXX 27 is Operable Operable when fXT is selected as count clock selected as count clock Watchdog timer Operable Operation stops A D converter Operable Operatio...

Page 518: ... 2 HALT Mode Clear upon Interrupt Request Generation Remarks 1 The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged 2 Wait time will be as follows When vectored interrupt service is carried out 8 to 9 clocks When vectored interrupt service is not carried out 2 to 3 clocks b Clear upon non maskable interrupt request When an unmasked inte...

Page 519: ...MK PR IE ISP Operation Maskable interrupt 0 0 0 Next address instruction execution request 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrupt service execution 1 HALT mode hold Non maskable interrupt Interrupt service execution request Test input 0 Next address instruction execution 1 HALT mode hold RESET input Reset processing Remark x Don t care ...

Page 520: ...ng Status Setting of STOP Mode With Subsystem Clock Without Subsystem Clock Item Clock generator Only main system clock stops oscillation CPU Operation stops Port output latch Status before STOP mode setting is held 16 bit timer event counter Operable when watch timer output is Operation stops selected as count clock fXT is selected as count clock of watch timer 8 bit timer event counter Operable ...

Page 521: ...ed interrupt request If interrupt acknowledge is enabled vectored interrupt servicing is performed after the lapse of the oscillation stabilization time If interrupt acknowledge is disabled the next address instruction is executed Figure 23 4 STOP Mode Release by Interrupt Request Generation Remark The broken line indicates the case when the interrupt request which has cleared the standby status i...

Page 522: ...ime reset operation is performed Figure 23 5 Release by STOP Mode RESET Input Remarks 1 fX main system clock oscillation frequency 2 fX 5 0 MHz Table 23 4 Operation After STOP Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt service execution 0 1 0 1 Next address instruction execution 0 1 0 0 1 1 1 Interrupt serv...

Page 523: ...ach pin has high impedance during reset input or during oscillation stabilization time just after reset clear When a high level is input to the RESET input the reset is cleared and program execution starts after the lapse of oscillation stabilization time 217 fX The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscil...

Page 524: ...t Pin Delay Delay Hi Z X1 Normal Operation Reset Period Oscillation Stop Oscillation Stabilization Time Wait Normal Operation Reset Processing X1 Normal Operation Watchdog Timer Overflow Internal Reset Signal Port Pin Reset Period Oscillation Stop Oscillation Stabilization Time Wait Normal Operation Reset Processing Hi Z Figure 24 2 Timing of Reset Input by RESET Input Figure 24 3 Timing of Reset ...

Page 525: ...tabilization time select register OSTS 04H 16 bit timer event counter Timer register TM0 00H Capture compare register CR00 CR01 Undefined Clock selection register TCL0 00H Mode control register TMC0 00H Capture compare control register 0 CRC0 04H Output control register TOC0 00H 8 bit timer event counter Timer register TM1 TM2 00H Compare registers CR10 CR20 Undefined Clock select register TCL1 00...

Page 526: ...or control register BRGC 00H Transmit shift register TXS Receive buffer register RXB Interrupt timing specify register SINT 00H A D converter Mode register ADM 01H Conversion result register ADCR Undefined Input select register ADIS 00H D A converter Mode register DAM 00H Conversion value setting register DACS0 DACS1 00H Real time output port Mode register RTPM 00H Control register RTPC 00H Buffer...

Page 527: ...flow can be changed by using the ROM correction The ROM correction can correct two places max of the internal ROM program Caution The ROM correction cannot be emulated by the in circuit emulator IE 78000 R IE 78000 R A IE 78K0 NS and IE 78001 R A 25 2 ROM Correction Configuration The ROM correction is executed by the following hardware Table 25 1 ROM Correction Configuration Item Configuration Reg...

Page 528: ...egisters 0 and 1 Format Cautions 1 Set the CORAD0 and CORAD1 when bit 1 COREN0 and bit 3 COREN1 of the correction control register CORCN see Figure 25 3 are 0 2 Only addresses where operation codes are stored can be set in CORAD0 and CORAD1 3 Do not set the following addresses to CORAD0 and CORAD1 Address value in table area of table reference instruction CALLT instruction 0040H to 007FH Address v...

Page 529: ...trol Registers The ROM correction is controlled with the correction control register CORCN 1 Correction control register CORCN This register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1 The correction control register consists of correction enable flags COREN0 COREN1 and c...

Page 530: ...t program as well The branch destination judgment program checks which one of the addresses set to correction address register 0 1 CORAD0 or CORAD1 generates the correction branch Figure 25 4 Storing Example to EEPROM When One Place Is Corrected Figure 25 5 Connecting Example with EEPROM Using 2 Wire Serial I O Mode RA78K 0 EEPROM Source program 00 10 0D 02 9B 02 10 00H 01H 02H FFH CSEG AT 1000H A...

Page 531: ...on to be corrected to CORAD0 and CORAD1 and set bits 1 and 3 COREN0 COREN1 of the correction control register CORCN to 1 4 Set the entire space branch instruction BR addr16 to the specified address F7FDH of the internal expansion RAM with the main program 5 After the main program is started the fetch address value and the values set in CORAD0 and CORAD1 are always compared by the comparator in the...

Page 532: ...No Yes Internal ROM program start Does fetch address match with correction address Set correction status flag Correction branch branch to address F7FDH Correction program execution ROM correction Figure 25 7 ROM Correction Operation ...

Page 533: ... is changed to ADD A 2 is as follows Figure 25 8 ROM Correction Example 1 Branches to address F7FDH when the preset value 1000H in the correction address register 0 1 CORAD0 CORAD1 matches the fetch address value after the main program is started 2 Branches to any address address F702H in this example by setting the entire space branch instruction BR addr16 to address F7FDH with the main program 3...

Page 534: ...nd 25 10 show the program transition diagrams when the ROM correction is used Figure 25 9 Program Transition Diagram When One Place Is Corrected 1 Branches to address F7FDH when fetch address matches correction address 2 Branches to correction program 3 Returns to internal ROM program Remark Area filled with diagonal lines Internal expansion RAM JUMP Correction program start address ...

Page 535: ...atches correction address 2 Branches to branch destination judgment program 3 Branches to correction program 1 by branch destination judgment program BTCLR CORST0 xxxxH 4 Returns to internal ROM program 5 Branches to address F7FDH when fetch address matches correction address 6 Branches to branch destination judgment program 7 Branches to correction program 2 by branch destination judgment program...

Page 536: ...the set address value 3 Do not set the address value of instruction immediately after the instruction that sets the correction enable flag COREN0 COREN1 to 1 to correction address register 0 or 1 CORAD0 CORAD1 the correction branch may not start 4 Do not set the address value in table area of table reference instruction CALLT instruction 0040H to 007FH and the address value in vector table area 00...

Page 537: ...ching register Changing of internal expansion RAM EnableNote 2 Disable capacity by internal expansion RAM size switching register IC pin None Available VPP pin Available None Pins P60 to P63 pull resistance on chip None Available mask option Electrical characteristics Refer to the separate Data Sheet Notes 1 Through the RESET input the internal PROM capacity becomes 60 Kbytes and the internal high...

Page 538: ...D78058F 78P058F 78058FY and 78P058FY the capacity of the internal ROM should be less than 56 Kbytes The IMS settings to give the same memory map as mask ROM versions are shown in Table 26 2 Table 26 2 Examples of Memory Size Switching Register Settings Relevant Mask ROM Version IMS Setting µPD78056F 78056FY CCH µPD78058F 78058FY CFH 7 RAM2 Symbol IMS 6 RAM1 5 RAM0 4 0 3 ROM3 2 ROM2 1 ROM1 0 ROM0 A...

Page 539: ...ing that is the same as that of mask ROM products with different internal expansion RAM The IXS is set by an 8 bit memory manipulation instruction RESET signal input sets IXS to 0AH Figure 26 2 Internal Expansion RAM Size Switching Register Format The value in the IXS that has the identical memory map to the mask ROM versions is given in Table 26 3 Table 26 3 Value Set to the Internal Expansion RA...

Page 540: ...VPP pin and a low level signal is applied to the RESET pin the µPD78P058F and µPD78P058FY are set to the PROM programming mode This is one of the operating modes shown in Table 26 4 below according to the setting of the CE OE and PGM pins The PROM contents can be read by setting the read mode Table 26 4 PROM Programming Operating Modes Pin Operating Mode Page data latch H L H Data input Page write...

Page 541: ...rite and verify operations are executed X times X 10 6 Byte write mode A byte write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE L and OE H After this program verification can be performed by setting OE to L If programming is not performed by one program pulse repeated write and verify operations are executed X times X 10 7 Program verify mode Setting CE to L P...

Page 542: ...P 12 5 V X 0 Latch Address Address 1 Latch Address Address 1 Latch Address Address 1 Latch X X 1 0 1 ms program pulse Verify 4 Bytes Pass Address N No Pass VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Address Address 1 No Yes X 10 Fail Fail Yes All Pass Defective product Remark G Start address N Last address of program ...

Page 543: ... µPD78P058F 78P058FY Page Data Latch Page Program Program Verify Data Input Data Output Hi Z A2 to A16 A0 A1 D0 to D7 VPP VDD VPP VDD 1 5 VDD VDD VIH CE PGM OE VIL VIH VIL VIH VIL Figure 26 4 Page Program Mode Timing ...

Page 544: ... Start Address G VDD 6 5 V VPP 12 5 V X 0 X X 1 0 1 ms program pulse Verify Address N VDD 4 5 to 5 5 V VPP VDD All bytes verified End of write Fail Fail Pass Yes All Pass No Pass Defective product No Yes X 10 Address Address 1 Remark G Start address N Last address of program ...

Page 545: ...DD CE PGM OE Figure 26 6 Byte Program Mode Timing Cautions 1 Be sure to apply VDD before applying VPP and remove it after removing VPP 2 VPP must not exceed 13 5 V including overshoot voltage 3 Disconnecting inserting the device from to the on board socket while 12 5 V is being applied to the VPP pin may have an adverse affect on device reliability ...

Page 546: ...1 Fix the RESET pin low and supply 5 V to the VPP pin Unused pins are handled as shown in paragraph 2 PROM programming mode in section 1 5 or 2 5 Pin Configuration Top View 2 Supply 5 V to the VDD and VPP pins 3 Input the address of data to be read to pins A0 through A16 4 Read mode is entered 5 Data is output to pins D0 through D7 The timing for steps 2 through 5 above is shown in Figure 26 7 Fig...

Page 547: ...hipment due to the structure of one time PROM Therefore after users have written data into the PROM screening should be implemented by user that is store devices at high temperature for one day as specified below and verify their contents after the devices have returned to room temperature Storage Temperature Storage Time 125 C 24 hours ...

Page 548: ...548 MEMO ...

Page 549: ... SET This chapter describes each instruction set of the µPD78058F and 78058FY Subseries as list table For details of its operation and operation code refer to the separate document 78K 0 Series USER S MANUAL Instructions U12326E ...

Page 550: ...unction names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 27 1 Operand Identifiers and Description Methods Identifier Description Method r X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RP0 BC RP1 DE RP2 HL RP3 sfr Special function register symbolNote sfrp Special function register symbol 16 bit manipulatable register even addre...

Page 551: ...ry carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents in parentheses H L Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit...

Page 552: ...ote 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 n m A addr16 XCH A DE 1 4 6 n m A DE A HL 1 4 6 n m A HL A HL byte 2 8 10 n m A HL byte A HL B 2 8 10 n m A HL B A HL C 2 8 10 n m A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remarks 1 One instruc...

Page 553: ...r CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 n A CY A addr16 CY A HL 1 4 5 n A CY A HL CY A HL byte 2 8 9 n A CY A HL byte CY A HL B 2 8 9 n A CY A HL B CY A HL C 2 8 9 n A CY A HL C CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area ...

Page 554: ... HL B CY A HL C 2 8 9 n A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 n A A addr16 A HL 1 4 5 n A A HL A HL byte 2 8 9 n A A HL byte A HL B 2 8 9 n A A HL B A HL C 2 8 9 n A A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the int...

Page 555: ...A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 n A addr16 A HL 1 4 5 n A HL A HL byte 2 8 9 n A HL byte A HL B 2 8 9 n A HL B A HL C 2 8 9 n A HL C Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed 3 Except r A Remar...

Page 556: ... CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 n CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit CY A bit CY 2 4 A bit CY PSW bit CY 3 8 PSW bit CY HL bit CY 2 6 8 n m HL bit CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock is the l...

Page 557: ... 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 n m HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 CLR1 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 HL bit 2 6 8 n m HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 On...

Page 558: ...PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ addr16 2 6 PC PC 2 jdisp8 if Z 0 Notes 1 When the internal high speed RAM area is accessed or instruction with no data access 2 When an area except the internal high speed RAM area is accessed Remarks 1 One instruction clock is the length of 1 clock cycle of the CPU clock ...

Page 559: ...t A bit PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit PC PC 3 jdisp8 if HL bit 1 then reset HL bit B B 1 then PC PC 2 jdisp8 if B 0 C C 1 then PC PC 2 jdisp8 if C 0 saddr saddr 1 then PC PC 3 jdisp8 if saddr 0 SEL RBn 2 4 RBS1 0 n NOP 1 2 No Operation EI 2 6 IE 1 Enable Interrupt DI 2 6 IE 0 Disable Interrupt HALT 2 6 Set HALT Mode STOP 2 6 Set STOP Mode Notes 1 When the internal high speed RAM a...

Page 560: ...560 CHAPTER 27 INSTRUCTION SET 27 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 PUSH POP DBNZ ...

Page 561: ...DD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP addr16 MOV PSW MOV MOV PUSH POP DE MOV HL MOV ROR4 ROL4 HL byte MOV HL B HL C X MU...

Page 562: ...HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit MOV1 BT SET1 BF CLR1 BTCLR sfr bit MOV1 BT SET1 BF CLR1 BTCLR saddr bit MOV1 BT SET1 BF CLR1 BTCLR PSW bit MOV1 BT SET1 BF CLR1 BTCLR HL bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1 wor...

Page 563: ...tions branch instructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 564: ...564 MEMO ...

Page 565: ...F 60 Kbytes µPD780055 40 Kbytes µPD78P054 32 Kbytes µPD780056 48 Kbytes µuPD78056 48 Kbytes µPD780058 60 Kbytes µPD78058 60 Kbytes µPD78F0058 60 Kbytes µPD78P058 60 Kbytes Internal high speed RAM size µPD78052 512 bytes 1024 bytes 1024 bytes µPD78053 78054 78P054 78056 78058 78P058 1024 bytes I O port Total 69 Total 68 CMOS input 2 CMOS input 2 CMOS input output 63 CMOS input output 62 N ch open d...

Page 566: ...P 80 pin plastic QFP 80 pin plastic QFP 14 14 mm Resin 14 14 mm Resin 14 14 mm Resin thickness 2 7 mm thickness 2 7 mm thickness 2 7 mm 80 pin plastic QFP 80 pin plastic QFP 80 pin plastic QFP 14 14 mm Resin 14 14 mm Resin 14 14 mm Resin thickness 1 4 mm thickness 1 4 mm thickness 1 4 mm 80 pin ceramics WQFN 80 pin plastic TQFP 80 pin plastic TQFP 14 14 mm µPD78P054 Fine pitch 12 12 mm Fine pitch ...

Page 567: ...NDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the µPD78058F and 78058FY Subseries Figure B 1 shows the configuration of the development tools ...

Page 568: ...are Assembler package C compiler package C library source file Device file Tool for PROM writing PG 1500 controller Embeded software Real time OS OS Host machine PC Interface adapter PC card interface etc Target system Emulation board Emulation probe Power supply unit Conversion socket or conversion adapter In circuit emulator PROM writing environment PROM programmer Product with on chip PROM Prog...

Page 569: ...ted debugger Device file Language processing software Assembler package C compiler package C library source file Device file Tool for PROM writing PG 1500 controller Embeded software Real time OS OS Host machine PC or EWS Interface board Target system Interface adapter Emulation board I O board Probe board Emulation probe conversion board Emulation probe Conversion socket In circuit emulator PROM ...

Page 570: ...r µS CC78K0 DF78054Note File containing information peculiar to the device Device file Used in combination with optional tools RA78K 0 CC78K 0 SM78K0 ID78K0 NS or ID78K0 Compatible OS and host machine differ depending on tools to be used Part number µS DF78054 CC78K 0 L Source program of functions for generating object library included in C C library source file compiler package Necessary for chan...

Page 571: ...grammer the PG 1500 adapter PA 78P054GC 80 pin plastic QFP GC 3B9 GC 8BT type B 2 2 Software PG 1500 controller This program controls the PG 1500 from the host machine through serial and or parallel interface cable s The PG 1500 controller is a DOS based application When using Windows start it from the DOS prompt Part Number µS PG1500 Remark of the part number differs depending on the host machine...

Page 572: ...E 78K0 NS host machine IE 780308 NS EM1Note This board emulates the operations of the peripheral hardware peculiar to Emulation board a device It should be used in combination with an in circuit emulator NP 80GC This probe is used to connect the in circuit emulator to the target system Emulation probe and is designed for 80 pin plastic QFP GC 3B9 GC 8BT types EV 9200GC 80 This conversion socket co...

Page 573: ...and emulation probe conversion IE 78K0 R EX1Note 1 This board is required when using the IE 780308 NS EM1 with the Emulation probe IE 78001 R A conversion board IE 78064 R EMNote 2 This is a board for emulation of peripheral hardware inherent to this device IE 780308 R EM IE 78064 R EM is for 3 0 to 6 0 V and IE 780308 R EM is for 2 0 to 5 0 V Emulation board Use in combination with a IE 78001 R A...

Page 574: ...it emulator independently of hardware development so that development efficiency and software quality can be improved This simulator is used with optional device file DF78054 Part Number µS SM78K0 Remark of the part number differs depending on the host machine and OS used Refer to the table below µS SM78K0 Host Machine OS Supply Media AA13 PC 9800 Series Windows Japanese Note 3 5 inch 2HD FD AB13 ...

Page 575: ...rcuit by incorporating function expansion modules such as a task debugger and emulator IE 78001 R A system performance analyzer This debugger is used in combination with an optional device file DF78054 Part number µS ID78K0 NS µS ID78K0 Note Under development Remark in the part number differs depending on the host machine and OS used µS ID78K0 NS Host Machine OS Supply Media AA13 PC 9800 Series Wi...

Page 576: ...oftware B 5 Upgrading Former In circuit Emulators for 78K 0 Series to IE 78001 R A If you have a former in circuit emulator for the 78K 0 Series IE 78000 R or IE 78000 R A your in circuit emulator can be upgraded to be equivalent to the IE 78001 R A in circuit emulator by simply replacing the break board with the IE 78001 R BK under development Table B 2 Upgrading Former In circuit Emulator for 78...

Page 577: ...0GC 80 B C M N O L K S R Q P I H J G EV 9200GC 80 G1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M N O P Q R S 18 0 14 4 14 4 18 0 4 C 2 0 0 8 6 0 16 0 18 7 6 0 16 0 18 7 8 2 8 0 2 5 2 0 0 35 2 3 1 5 0 709 0 567 0 567 0 709 4 C 0 079 0 031 0 236 0 63 0 736 0 236 0 63 0 736 0 323 0 315 0 098 0 079 0 014 0 091 0 059 φ φ Based on EV 9200GC 80 1 Package drawing in mm φ φ ...

Page 578: ...776 0 591 0 591 0 776 0 236 0 236 0 014 0 093 0 091 0 062 0 65 0 02 19 12 35 0 05 0 65 0 02 19 12 35 0 05 φ φ φ 0 002 0 001 0 003 0 002 0 002 0 001 0 003 0 002 0 004 0 003 0 004 0 003 0 001 0 002 φ φ φ 0 001 0 002 0 001 0 002 Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVI...

Page 579: ... 047 R 1 58 0 062 S 3 55 0 140 N 1 58 0 062 O 1 2 P 7 64 0 301 0 047 W 6 8 0 268 X 8 24 0 324 Y 14 8 0 583 T C 2 0 C 0 079 U 12 31 V 10 17 0 400 0 485 Z 1 4 0 2 0 055 0 008 0 5 1 58 0 020 0 062 G 18 0 0 709 k 3 0 0 118 n 1 4 0 2 0 055 0 008 o 1 4 0 2 0 055 0 008 p h 1 8 1 3 h 0 071 0 051 l 0 25 m 14 0 0 551 0 010 q 0 5 0 000 0 197 φ φ 11 77 0 5 φ 0 463 0 020 φ TGK 080SDW G0E t 2 4 0 094 u 2 7 0 10...

Page 580: ...580 MEMO ...

Page 581: ...ENDIX C EMBEDDED SOFTWARE This chapter describes the embedded software that is available for the µPD78058F and 78058FY Subseries to allow users to develop and maintain application programs for these subseries ...

Page 582: ...nce Remark The part numbers and differ depending on the host machine and OS used Notes 1 Can be operated in DOS environment 2 Does not support WindowsNT S01 001 100K 001M 010M Product Outline Upper Limit of Quantity for Mass Production Evaluation object Do not use for mass produced product Source program for mass produced object 0 1 million 1 million 10 million Source program Object for mass produ...

Page 583: ...achine and OS used Notes 1 Can be operated in DOS environment 2 Does not support WindowsNT 001 S01 Product Outline Upper Limit of Quantity for Mass Production Evaluation object Use for trial product Use for mass produced product Can be purchased only when object for mass produced product is purchased S MX78K0 µ Object for mass produced product Source program 3K13 3P16 HP9000 series 700 AA13 AB13 B...

Page 584: ...584 MEMO ...

Page 585: ...e register 01 CR01 177 Compare registers 10 CR10 219 Compare registers 20 CR20 219 Correction address register 0 CORAD0 528 Correction address register 1 CORAD1 528 Correction control register CORCN 529 D D A conversion value set register 0 DACS0 281 D A conversion value set register 1 DACS1 281 D A converter mode register DAM 282 E 8 bit timer mode control register TMC1 222 8 bit timer output con...

Page 586: ...t mode register 12 PM12 130 146 474 Port mode register 13 PM13 130 146 Port mode register 2 PM2 130 146 Port mode register 3 PM3 130 146 184 224 256 260 Port mode register 5 PM5 130 146 Port mode register 6 PM6 130 146 Port mode register 7 PM7 130 146 Priority specify flag register 0H PR0H 485 Priority specify flag register 0L PR0L 485 Priority specify flag register 1L PR1L 485 Processor clock con...

Page 587: ... 178 254 Timer clock select register 1 TCL1 220 Timer clock select register 2 TCL2 240 248 258 Timer clock select register 3 TCL3 292 345 391 Transmit shift register TXS 437 W Watch timer mode control register TMC2 243 Watchdog timer mode register WDTM 250 D 2 Register Index Register Symbol A ADCR A D conversion result register 264 ADIS A D converter input select register 267 ADM A D converter mod...

Page 588: ...H 483 IF0L Interrupt request flag register 0L 483 IF1L Interrupt request flag register 1L 483 503 IMS Memory size switching register 509 538 INTM0 External interrupt mode register 0 185 486 INTM1 External interrupt mode register 1 268 486 IXS Internal expansion RAM size switching register 539 K KRM Key return mode register 151 504 M MK0H Interrupt mask flag register 0H 484 MK0L Interrupt mask flag...

Page 589: ...ster 475 RTPM Real time output port mode register 474 RXB Receive buffer register 437 RXS Receive shift register 437 S SAR Successive approximation register 264 SBIC Serial bus interface control register 296 302 314 333 349 355 360 369 SCS Sampling clock select register 186 488 SFR Special function register 108 SINT Interrupt timing specify register 298 316 351 360 370 SIO0 Serial I O shift regist...

Page 590: ...590 APPENDIX D REGISTER INDEX TOC1 8 bit timer output control register 223 TXS Transmit shift register 437 W WDTM Watchdog timer mode register 250 ...

Page 591: ...0 CHAPTER 16 SERIAL was added INTERFACE CHANNEL 0 Note related to BSYE in Figure 16 5 Serial Bus Interface Control Register µPD78058F SUBSERIES Format was changed Cautions were added to 16 4 3 2 a Bus release signal REL and b Command signal CMD CSCK was deleted from Figure 19 1 Serial Interface Channel 2 Block Diagram CHAPTER 19 SERIAL and Figure 19 2 Baud Rate Generator Block Diagram INTERFACE CH...

Page 592: ...592 MEMO ...

Page 593: ...x 02 719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6465 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 548 7900 I ...

Search results

Summary of Contents for PD78056F

Reviews:

Related manuals for PD78056F

Brands by name

Popular brands

NEC PD78056F, User Manual

Search results

Summary of Contents for PD78056F

Reviews:

Related manuals for PD78056F

Brands by name

Popular brands