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CHAPTER 3

FEATURES OF THE ARCHITECTURE AND MEMORY MAP .......................................

3.1

DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES ..................

3.1.1

Data Memory Bank Structure ....................................................................

3.1.2

Data Memory Addressing Modes ..............................................................

3.2

GENERAL REGISTER BANK CONFIGURATION .................................................

3.3

MEMORY-MAPPED I/O ..........................................................................................

CHAPTER 4

INTERNAL CPU FUNCTIONS .........................................................................................

4.1

Mk I MODE/Mk II MODE SWITCH FUNCTIONS ...................................................

4.1.1

Differences between Mk I Mode and Mk II Mode .....................................

4.1.2

Setting of the Stack Bank Selection Register (SBS) ................................

4.2

PROGRAM COUNTER (PC) .................................................................................

4.3

PROGRAM MEMORY (ROM) ................................................................................

4.4

DATA MEMORY (RAM) ..........................................................................................

4.4.1

Data Memory Configuration.......................................................................

4.4.2

Specification of a Data Memory Bank .......................................................

4.5

GENERAL REGISTER ............................................................................................

4.6

ACCUMULATOR .....................................................................................................

4.7

STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ............

4.8

PROGRAM STATUS WORD (PSW) ......................................................................

4.9

BANK SELECT REGISTER (BS) ...........................................................................

CHAPTER 5

PERIPHERAL HARDWARE FUNCTIONS ......................................................................

5.1

DIGITAL I/O PORTS .............................................................................................

5.1.1

Types, Features, and Configurations of Digital I/O Ports ........................

5.1.2

I/O Mode Setting ........................................................................................

5.1.3

Digital I/O Port Manipulation Instructions .................................................

5.1.4

Digital I/O Port Operation ..........................................................................

5.1.5

Specification of Bilt-in Pull-Up Resistors ..................................................

5.1.6

I/O Timing of Digital I/O Ports ...................................................................

5.2

CLOCK GENERATOR ............................................................................................

5.2.1

Clock Generator Configuration ..................................................................

5.2.2

Functions and Operations of the Clock Generator ...................................

5.2.3

System Clock and CPU Clock Setting ......................................................

5.2.4

Clock Output Circuit ...................................................................................

5.3

BASIC INTERVAL TIMER/WATCHDOG TIMER ...................................................

5.3.1

Configuration of the Basic Interval Timer/Watchdog Timer .....................

5.3.2

Basic Interval Timer Mode Register (BTM) ..............................................

5.3.3

Watchdog Timer Enable Flag (WDTM) ..................................................... 101

5.3.4

Operation of the Basic Interval Timer ....................................................... 101

Summary of Contents for PD750004

Page 1: ...750008 4 BIT SINGLE CHIP MICROCOMPUTER 1995 USER S MANUAL µPD750004 µPD750006 µPD750008 µPD75P0016 Document No U10740EJ2V0UM00 2nd edition Previous No IEU 1421 Date Published April 1996 P Printed in Japan ...

Page 2: ...T FUNCTIONS PERIPHERAL HARDWARE FUNCTIONS INTERNAL CPU FUNCTIONS PIN FUNCTIONS A B C 11 D E F RIVISION HISTORY HARDWARE INDEX INSTRUCTION INDEX MASK ROM ORDERING PROCEDURE DEVELOPMENT TOOLS FUNCTIONS OF THE µPD75008 µPD750008 AND µPD75P0016 INSTRUCTION SET WRITING TO AND VERIFYING PROGRAM MEMORY PROM STANDBY FUNCTION ...

Page 3: ...efect in an NEC semiconductor device customer must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific appl...

Page 4: ... Mk II mode has been added in Section 4 1 1 p 85 The description for the mask option when using the feedback resistor has been added in 6 in Section 5 2 2 p 187 The description for the interrupt enable flag has been added in Section 6 3 p 198 Table 6 4 has been added in Section 6 6 p 233 Section 9 4 has been added p 235 Chapter 10 has been added p 237 298 The operand rpa has been changed to rpa1 i...

Page 5: ...t and test functions Standby function Reset function Writing to and verifying program memory PROM Mask option Instruction set Guidance Readers of this manual should have general knowledge of the electronics logical circuit and microcomputer fields For users who have used the µPD75008 See Appendix A to check for any difference in the functions and read the explanation of those differences To check ...

Page 6: ... Memory map address Low order address on the upper side High order address on the lower side Note Explanation of an indicated part of text Caution Information requesting the user s special attention Remark Supplementary information Important and emphasized matter Described in bold face Numeric value Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH ...

Page 7: ...ual EEU 698 EEU 1305 PG 1500 User s Manual EEU 651 EEU 1335 Software RA75X Assembler Package User s Operation EEU 731 EEU 1346 Manual Language EEU 730 EEU 1363 PG 1500 Controller PC 9800 Series MS DOSTM Base EEU 704 EEU 1291 User s Manual IBM PC Series PC DOSTM Base EEU 5008 U10540E Other documents Document Name Document Number Japanese English Package Manual IEI 635 IEI 1213 Semiconductor Device ...

Page 8: ... MEMO ...

Page 9: ...RT3 13 P40 P43 PORT4 P50 P53 PORT5 13 P60 P63 PORT6 P70 P73 PORT7 13 2 2 3 P80 P81 PORT8 13 2 2 4 TI0 13 2 2 5 PTO0 PTO1 13 2 2 6 PCL 14 2 2 7 BUZ 14 2 2 8 SCK SO SB0 SI SB1 14 2 2 9 INT4 14 2 2 10 INT0 INT1 14 2 2 11 INT2 15 2 2 12 KR0 KR3 15 KR4 KR7 15 2 2 13 X1 X2 15 2 2 14 XT1 XT2 16 2 2 15 RESET 16 2 2 16 VDD 16 2 2 17 VSS 16 2 2 18 IC for the µPD750004 µPD750006 and µPD750008 only 17 2 2 19 ...

Page 10: ... STACK BANK SELECT REGISTER SBS 58 4 8 PROGRAM STATUS WORD PSW 62 4 9 BANK SELECT REGISTER BS 65 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 67 5 1 DIGITAL I O PORTS 67 5 1 1 Types Features and Configurations of Digital I O Ports 68 5 1 2 I O Mode Setting 74 5 1 3 Digital I O Port Manipulation Instructions 76 5 1 4 Digital I O Port Operation 79 5 1 5 Specification of Bilt in Pull Up Resistors 81 5 1 6...

Page 11: ...Pin Output 179 5 7 BIT SEQUENTIAL BUFFER 181 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 183 6 1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT 183 6 2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES 185 6 3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS 187 6 4 INTERRUPT SEQUENCE 195 6 5 MULTIPLE INTERRUPT PROCESSING CONTROL 196 6 6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS 198 6 7 MACHINE CYCLES...

Page 12: ...s 239 11 1 5 Skip Instructions and the Number of Machine Cycles Required for a Skip 240 11 2 INSTRUCTION SET AND OPERATION 241 11 3 INSTRUCTION CODES OF EACH INSTRUCTION 258 11 4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS 264 11 4 1 Transfer Instructions 264 11 4 2 Table Reference Instructions 270 11 4 3 Bit Transfer Instructions 273 11 4 4 Arithmetic Logical Instructions 273 11 4 5 Accumulato...

Page 13: ...DURE 309 APPENDIX D INSTRUCTION INDEX 311 D 1 INSTRUCTION INDEX BY FUNCTION 311 D 2 INSTRUCTION INDEX ALPHABETICAL ORDER 314 APPENDIX E HARDWARE INDEX 317 E 1 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME 317 E 2 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL 319 APPENDIX F REVISION HISTORY 321 ...

Page 14: ...ogram Memory Map in µPD75P0016 52 4 7 Data Memory Map 54 4 8 General Register Format 56 4 9 Register Pair Format 57 4 10 Accumulator 57 4 11 Format of Stack Pointer and Stack Bank Select Register 59 4 12 Data Saved to the Stack Memory Mk I Mode 59 4 13 Data Restored from the Stack Memory Mk I Mode 60 4 14 Data Saved to the Stack Memory Mk II Mode 60 4 15 Data Restored from the Stack Memory Mk II M...

Page 15: ...ormat of the Basic Interval Timer Mode Register 100 5 25 Format of the Watchdog Timer Enable Flag WDTM 101 5 26 Block Diagram of the Clock Timer 106 5 27 Clock Mode Register Format 107 5 28 Block Diagram of the Timer Event Counter Channel 0 109 5 29 Block Diagram of the Timer Counter Channel 1 110 5 30 Timer Event Counter Mode Register Channel 0 Format 112 5 31 Timer Counter Mode Register Channel ...

Page 16: ...ACKT 162 5 63 Operation of ACKE 162 5 64 Operation of ACKD 163 5 65 Operation of BSYE 164 5 66 Pin Configuration 167 5 67 Address Transfer Operation from Master Device to Slave Device WUP 1 169 5 68 Command Transfer Operation from Master Device to Slave Device 170 5 69 Data Transfer Operation from Master Device to Slave Device 171 5 70 Data Transfer Operation from Slave Device to Master Device 172...

Page 17: ...nterrupt Sequence 195 6 8 Multiple Interrupt Processing by a High Order Interrupt 196 6 9 Multiple Interrupt Processing by Changing the Interrupt Status Flags 197 6 10 Block Diagram of the INT2 and KR0 to KR7 Circuits 212 6 11 Format of INT2 Edge Detection Mode Register IM2 213 7 1 Standby Mode Release Operation 218 7 2 Wait Time When the STOP Mode Is Released 219 8 1 Configuration of Reset Functi...

Page 18: ...nk to Be Selected with the RBE and RBS 66 5 1 Types and Features of Digital Ports 68 5 2 I O Pin Manipulation Instructions 78 5 3 Operations by I O Port Manipulation Instructions 80 5 4 Specification of Built in Pull Up Resistors 81 5 5 Maximum Time Required to Change the System Clock and CPU Clock 94 5 6 Resolution and Longest Setup Time 117 5 7 Serial Clock Selection and Application In the Three...

Page 19: ...ST OF TABLES 2 2 Table No Title Page 7 1 Operation Statuses in the Standby Mode 216 7 2 Selection of a Wait Time with BTM 219 8 1 Status of the Hardware after a Reset 226 10 1 Selecting Mask Option of Pin 235 ...

Page 20: ... xii MEMO ...

Page 21: ... µs 2 67 µs 10 7 µs at 6 0 MHz 122 µs at 32 768 kHz Enhanced timers 4 channels Easy replacement The functions and instructions of the µPD75008 are taken over The 75XL series comes in four models according to the size and type of program memory see Table 1 1 Table 1 1 Features of the Products Model Program memory ROM Remarks µPD750004 4096 x 8 bits Masked ROM µPD750006 6144 x 8 bits µPD750008 8192 ...

Page 22: ... specified with the mask option Note Timer 4 Timer event counter 1 channel Timer counter 1 channel Basic interval timer watchdog timer 1 channel Clock timer 1 channel Serial interface Three wire serial I O mode switchable between the start LSB and the start MSB Two wire serial I O mode SBI mode Bit sequential buffer 16 bits Clock output F 524 kHz 262 kHz 65 5 kHz when the main system clock operate...

Page 23: ...k DIP 600 mil Masked ROM µPD750006GB xxx 3BS MTXNote 44 pin plastic QFP 10 x 10 mm Masked ROM µPD750008CU xxx 42 pin plastic shrink DIP 600 mil Masked ROM µPD750008GB xxx 3BS MTXNote 44 pin plastic QFP 10 x 10 mm Masked ROM µPD75P0016CU 42 pin plastic shrink DIP 600 mil One time PROM µPD75P0016GB 3BS MTXNote 44 pin plastic QFP 10 x 10 mm One time PROM Note Code orders on and after April 1 1996 can...

Page 24: ... fX Selection to use Yes No feedback resistors Whether to enable feedback resistors can Use of feedback for subsystem clock be specified resistors is factory set Pin 6 9 CU P33 30 P33 MD3 P30 MD0 connection 23 26 GB 20 CU IC VPP 38 GB Others Noise immunity and noise radiation vary with the circuit scale and mask layout Note 217 fX 21 8 ms at 6 0 MHz 31 3 ms at 4 19 MHz 215 fX 5 46 ms at 6 0 MHz 7 ...

Page 25: ...NTT1 Clocked serial interface INTCSI Interrupt control Program counterNote 1 ROMNote 2 program memory ALU CY P00 P03 BANK Decode and control General register fX 2N Clock output control PCL P22 Clock divider Clock generator Sub Main Standby control XT1 XT2 X1 X2 VSS RESET VDD CPU clock IC VPP Note 3 SBS P80 P81 P10 P13 P20 P23 P30 P33 P40 P43 P50 P53 P60 P63 P70 P73 P30 MD0 Note 3 P33 MD3 INT4 KR0 ...

Page 26: ...e Remark µPD75P0016 XT1 XT2 RESET X1 X2 P33 MD3 P32 MD2 P31 MD1 P30 MD0 P81 P80 SI SB1 P03 SO SB0 P02 SCK P01 INT4 P00 TI0 P13 INT2 P12 INT1 P11 INT0 P10 IC VPP Note VDD VSS P40 P41 P42 P43 P50 P51 P52 P53 P60 KR0 P61 KR1 P62 KR2 P63 KR3 P70 KR4 P71 KR5 P72 KR6 P73 KR7 P20 PTO0 P21 PTO1 P22 PCL P23 BUZ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ...

Page 27: ...75P0016 P72 KR6 P71 KR5 P70 KR4 P63 KR3 P62 KR2 P61 KR1 P60 KR0 P53 P52 P51 P50 P13 TI0 P00 INT4 P01 SCK P02 SO SB0 P03 SI SB1 P80 P81 P30 MD0 P31 MD1 P32 MD2 P33 MD3 P73 KR7 P20 PTO0 P21 PTO1 P22 PCL P23 BUZ V DD IC V PP Note P10 INT0 P11 INT1 P12 INT2 NC NC P43 P42 P41 P40 V SS XT1 XT2 RESET X1 X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 ...

Page 28: ... P53 Port 5 INT0 1 4 External vectored interrupt 0 1 4 P60 P63 Port 6 INT2 External test input 2 P70 P73 Port 7 X1 2 Main system clock oscillation 1 2 P80 P81 Port 8 XT1 2 Subsystem clock oscillation 1 2 KR0 KR7 Key return NC No connection SCK Serial clock IC Internally connected SI Serial input VDD Positive power supply SO Serial output VSS Ground SB0 1 Serial bus 0 1 VPP Programming power supply...

Page 29: ...lt in pull up resistors can be connected P12 INT2 by software in units of 4 bits Only the P13 TI0 P10 INT0 pin is provided with noise elimination function P20 I O PTO0 4 bit I O port PORT2 x Input E B P21 PTO1 Built in pull up resistors can be connected P22 PCL by software in units of 4 bits P23 BUZ P30Note 2 I O MD0 Note 3 Programmable 4 bit I O port PORT3 x Input E B P31Note 2 MD1 Note 3 I O can...

Page 30: ...erifying higher 4 bits of program memory PROM P60 I O KR0 Programmable 4 bit I O port PORT6 O Input F A P61 KR1 I O can be specified bit by bit P62 KR2 Built in pull up resistors can be P63 KR3 connected by software in units of 4 bits P70 I O KR4 4 bit I O port PORT7 Input F A P71 KR5 Built in pull up resistors can be P72 KR6 connected by software in units of P73 KR7 4 bits P80 I O 2 bit input por...

Page 31: ...Asynchronous B C KR0 KR3 I O P60 P63 Parallel falling edge detection testable input Input F A KR4 KR7 I O P70 P73 Parallel falling edge detection testable input Input F A X1 X2 Input Connection pin to a crystal ceramic resonator for main system clock generation When external clock is used it is input to X1 and its inverted signal is input to X2 XT1 Input Connection pin to a crystal for subsystem c...

Page 32: ...pulse input TI0 for timer event counter Input is always enabled for each pin of ports 0 and 1 regardless of the operation status of the other function of the pin Schmitt triggered inputs are used for the input pin of port 0 and pins of port 1 to prevent malfunction due to noise In addition a noise eliminator is provided for P10 See 3 of Section 6 3 Port 0 can be connected with built in pull up res...

Page 33: ...ng pull up resistor specification register group A POGA For ports 4 and 5 the use of built in pull up resistors can be specified bit by bit by mask option Ports 4 and 5 and ports 6 and 7 can be paired respectively for 8 bit I O A RESET input clears the output latches in the ports places port n in the input mode output high impedance state and drives ports 4 and 5 high if pull up resistors are prov...

Page 34: ...of the serial operation mode registers CSIM A RESET signal stops serial interface operation and places these pins in the input port mode A Schmitt triggered input is used for each pin 2 2 9 INT4 Input Pin Used Also as Port 0 INT4 is an external vectored interrupt input pin which is rising edge active as well as falling edge active When a signal applied to this pin goes from low to high or from hig...

Page 35: ...put and can accept a signal with some high level width regardless of the operating clock of the CPU A RESET signal clears IM2 to 0 In this case the test flag IRQ2 is set by a rising edge on the INT2 pin The INT2 pin can also be used to release the STOP and HALT modes A Schmitt triggered input is used for this pin 2 2 12 KR0 KR3 Input Pins Used Also for Port 6 KR4 KR7 Input Pins Used Also for Port ...

Page 36: ...ith certain low level width is applied to the pin a RESET signal is generated to cause a system reset which has priority over any other operations The RESET signal is used for normal CPU initialize start operation and is also used to release the standby STOP or HALT mode A Schmitt triggered input is used for the RESET input pin 2 2 16 VDD This is the positive power supply pin 2 2 17 VSS This is th...

Page 37: ...ay occur between the IC pin and the VDD pin This may cause your program to malfunction Connect the IC pin to the VDD pin keeping the wiring as short as possible 2 2 19 VPP for the µPD75P0016 only This is a program voltage input pin for program memory PROM write verify operation For normal use connect this pin to VDD keeping the wiring as short as possible shown above 12 5 V is applied for PROM wri...

Page 38: ...the µPD750008 Figure 2 1 Pin Input Output Circuits 1 2 Type A Schmitt trigger input with hysteresis IN CMOS input buffer VDD IN P ch N ch Push pull output which can be set to high impedance output off for both P ch and N ch VDD P ch N ch OUT Data Output disable Type D Type B P U R Pull Up Resistor IN P ch P U R enable P U R VDD ...

Page 39: ...T VDD P ch P U R P U R enable Output disable P ch Data Output disable Output disable N ch P U R Pull Up Resistor N ch Withstand voltage 13 V IN OUT Data VDD Output disable P U R Mask option Note P U R VDD P ch Input instruction Input buffer with an intermediate withstand voltage of 13 V Pull up resistor that operates only when an input instruction is excuted valid at low voltage Note Data Output d...

Page 40: ...to VSS or VDD P02 SO SB0 P03 SI SB1 P10 INT0 P12 INT2 To be connected to VSS P13 TI0 P20 PTO0 Input state To be connected to VSS or P21 PTO1 VDD through a resistor P22 PCL Output state To be left open P23 BUZ P30 MD0 P33 MD3 Note P40 P43 P50 P53 P60 P63 P70 P73 P80 P81 XT1 To be connected to VSS or VDD XT2 To be left open IC VPP Note To be connected directly to VDD Note µPD75P0016 ...

Page 41: ...µPD750008 uses such a memory bank structure that the low order eight bits are specified with an instruction directly or indirectly and the high order four bits are used to specify a memory bank To specify a memory bank MB two hardware items are incorporated Memory bank enable flag MBE Memory bank select register MBS The MBS is a register used to select a memory bank and the register can be set to ...

Page 42: ...he contents of the MBE are automatically saved or restored at the time of subroutine processing so that the MBE can be freely modified during subroutine processing In interrupt processing the MBE is automatically saved or restored and when interrupt processing is started the contents of the MBE can be specified for the interrupt processing by setting the interrupt vector table This speeds up inter...

Page 43: ...address from 00H to 7FH is specified in the operand memory bank 0 MB 0 is always used When an address from 80H to FFH is specified memory bank 15 MB 15 is always used Accordingly both the data area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH can be addressed in the MBE 0 mode In the MBE 1 mode MB MBS and specifiable data memory space can be expanded This ad...

Page 44: ...ank enable flag Area for general register Data area Static RAM memory bank 0 Data area Static RAM memory bank 1 Not provided Peripheral hardware area memory bank 15 000H 01FH 020H 07FH 0FFH 100H 1FFH F80H FC0H FFFH mem mem bit MBE 0 MBE 1 MBE 0 MBE 1 HL H mem bit DE DL Stack address ing fmem bit pmem L MBS 15 MBS 15 MBS 0 MBS 0 MBS 1 MBS 1 SBS 0 SBS 1 ...

Page 45: ...ements the L register after addressing HL automatically decrements the L register after addressing DE Address specified by DE in memory bank 0 DL Address specified by DL in memory bank 0 8 bit register HL Address specified by MB and HL Contents of the L register is indirect an even address addressing In this case MB MBE MBS Bit fmem bit Bit specified by bit at the address specified by fmem manipul...

Page 46: ...ses 00H to 7FH of bank 0 Examples 1 The data contained in BUFF is output on port 5 BUFF EQU 11AH BUFF located at address 11AH SET1 MBE MBE 1 SEL MB1 MBS 1 MOV A BUFF A BUFF SEL MB15 MBS 15 OUT PORT5 A PORT5 A 2 Data on port 4 is entered and is saved in DATA1 DATA1 EQU 5FH DATA1 located at address 5FH CLR1 MBE MBE 0 IN A PORT4 A PORT4 MOV DATA1 A DATA1 A 3 8 bit direct addressing mem In this addres...

Page 47: ...he L register can be incremented or decremented by one in the automatic increment or automatic decrement mode each time an instruction is executed thus simplifying the program step Example The data at 50H to 57H is transferred to 110H to 117H DATA1 EQU 57H DATA2 EQU 117H SET1 MBE MBE 1 SEL MB1 MBS 1 MOV D DATA1 SHR4 D 5 MOV HL DATA2 AND 0FFH HL 17H LOOP MOV A DL A DL XCH A HL A HL L L 1 BR LOOP Th...

Page 48: ...ing Static RAM Addresses INCS D DECS D INCS L DECS L INCS D DECS D INCS E DECS E INCS H DECS H INCS L DECS L INCS H DECS H x 0H 0 x H F x H DL 4 bit transfer DE 4 bit transfer HL 4 bit manipulation 8 bit manipulation H mem bit Bit manipulation Direct addressing Bit manipulation 4 bit transfer 8 bit transfer x FH DECS DE INCS DE DECS HL INCS HL Automatic decrement Automatic increment ...

Page 49: ...count register T0 of timer event counter 0 is equal to the data at addresses 30H and 31H DATA EQU 30H CLR1 MBE MOV HL DATA MOV XA T0 XA Count register 0 SKE XA HL XA HL 2 The data memory of 00H to FFH is cleared to 0 CLR1 RBE CLR1 MBE MOV XA 00H MOV HL 04H LOOP MOV HL XA HL XA INCS HL INCS HL BR LOOP 6 Bit manipulation addressing This addressing mode is used to perform bit manipulations such as Bo...

Page 50: ... to FBFH where interrupt related hardware is mapped Hardware mapped to these data memory areas can freely perform bit manipulations in the direct addressing mode at any time regardless of MBS and MBE setting Examples 1 Value input to P02 is inverted and the result is output on P33 MOV1 CY PORT0 2 NOT1 CY MOV1 PORT3 3 CY 2 The timer 0 interrupt request flag IRQT0 is tested The request flag if set i...

Page 51: ...e the high order 10 bits of a 12 bit data memory address is directly specified in the operand and the low order two bits and bit address are indirectly specified using the L register Thus the use of the L register enables 16 bits four ports to be continuously manipulated This addressing mode again enables bit manipulation regardless of MBE and MBS setting Example Pulses are output on the bits in t...

Page 52: ...g the H register and the low order four bits and bit address are directly specified in the operand This addressing mode enables a wide variety of manipulations for each bit in the entire data memory space Example Bit 2 at address 32H FLAG3 is reset if both bit 3 at address 30H FLAG1 and bit 0 at address 31H FLAG2 are set to 0 or 1 FLAG1 EQU 30H 3 FLAG2 EQU 31H 0 FLAG3 EQU 32H 2 SEL MB0 MOV H FLAG1...

Page 53: ...ode can be used for register save restoration operation using the PUSH or POP instruction as well as save restoration operation in interrupt and subroutine processing Examples 1 A register is saved and restored in subroutine processing SUB PUSH XA PUSH HL PUSH BS Save MBS and RBS POP BS POP HL POP XA RET 2 The contents of the HL register pair are transferred to the DE register pair PUSH HL POP DE ...

Page 54: ... the RBE is automatically saved or restored and when interrupt processing is started the contents of the RBE can be specified for the interrupt processing by setting the interrupt vector table Therefore as indicated in Table 3 3 by selecting a register bank depending on whether the processing is normal or interrupt the general register need not be saved and restored for the level one interrupt pro...

Page 55: ...ments and decrements at a speed comparable to that of an 8 bit microcomputer and thereby enables to program using mainly general registers 1 When used as a 4 bit register When the general register area is used on a 4 bit basis eight general registers the X A B C D E H and L registers are available in the register bank specified with RB RBE RBS as shown in Figure 3 5 The A register functions as a 4...

Page 56: ...operations comparisons and increments decrements of 8 bit data The other register pairs perform transfers arithmetic logical operations comparisons and increments decrements with the accumulator The HL register pair functions mainly as a data pointer and the DE and DL register pairs function as an auxiliary data pointer Examples 1 INCS HL HL HL 1 skip at HL 00H ADDS XA BC XA XA BC skip at carry SU...

Page 57: ... Processing X H D B X H D B X H D B X H D B 01H 03H 05H 07H 09H 0BH 0DH 0FH 11H 13H 15H 17H 19H 1BH 1DH 1FH A L E C A L E C A L E C A L E C 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH Register bank 0 RBE RBS 0 Register bank 1 RBE RBS 1 Register bank 2 RBE RBS 2 Register bank 3 RBE RBS 3 ...

Page 58: ...ng XA HL DE BC XA HL DE BC 00H 02H 04H 06H 08H 0AH 0CH 0EH When RBE RBS 0 XA HL DE BC XA HL DE BC 00H 02H 04H 06H 08H 0AH 0CH 0EH When RBE RBS 1 XA HL DE BC XA HL DE BC 10H 12H 14H 16H 18H 1AH 1CH 1EH When RBE RBS 2 XA HL DE BC XA HL DE BC 10H 12H 14H 16H 18H 1AH 1CH 1EH When RBE RBS 3 ...

Page 59: ...it Direct addressing mode specifying mem with All hardware allowing 4 bit manipulation MBE 0 or MBE 1 MBS 15 manipulation Register indirect addressing mode specifying HL with MBE 1 MBS 15 8 bit Direct addressing mode specifying mem even address with All hardware allowing 8 bit manipulation MBE 0 or MBE 1 MBS 15 manipulation Register indirect addressing mode specifying HL with the L register contai...

Page 60: ... F85H F86H F8BH F98H Address b3 b2 b1 b0 Hardware name symbol R W 1 bit 4 bits 8 bits Remarks Number of bits that can be manipulated R W R Note 1 Bit manipulation addressing Stack pointer SP Register bank selection register RBS Bank selection register BS Memory bank selection register MBS Basic interval timer mode register BTM Basic interval timer BT WDTM Bit 0 is fixed to 0 Only bit 3 can be mani...

Page 61: ...rks Number of bits that can be manipulated Bit manipulation addressing Timer event counter mode register TM0 Timer event counter modulo register TMOD0 R W mem bit TOE0Note 1 W mem bit Timer event counter count register T0 R FAAH TOE1Note 2 W mem bit R W Timer counter mode register TM1 mem bit Timer counter count register T1 R FAEH Timer counter modulo register TMOD1 R W Bit write manipu lation is ...

Page 62: ...bled only for reading R W R W R W R W R fmem bit Bit sequential buffer 3 BSB3 IST1 Program status word PSW CY R R W R W R W fmem bit Interrupt priority select register IPS Processor clock control register PCC INT1 edge detection mode register IM1 Bits 3 2 and 1 are fixed to 0 R W FB6H INT2 edge detection mode register IM2 Bits 3 and 2 are fixed to 0 R W Bits 2 and 1 are fixed to 0 FBAH R W R W FBE...

Page 63: ...ll up resistor specification register group B POGB R W Clock output mode register CLOM FE2H Whether this location is read or write accessible de pends on the bit FE0H FE4H Note FE6H FE8H FECH R W PM33 Port mode register group A PMGA PM63 PM32 PM62 PM31 PM61 PM30 PM60 R W Port mode register group B PMGB PM7 PM2 PM5 PM4 FEEH R W Port mode register group C PMGC PM8 CMDD SBI control register SBIC BSYE...

Page 64: ...s at a time specify PORT6 or PORT7 FF0H FF1H FF2H FF3H FF4H FF5H FF6HNote 2 FF7HNote 2 FF8H Address b3 b2 b1 b0 Hardware name symbol R W 1 bit 4 bits 8 bits Remarks Number of bits that can be manipulated R W R R W R W R W R W R W R W R W Bit manipulation addressing fmem bit pmem L Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 8 KR3 KR2 KR1 PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT8 KR0 Port 6 KR7 ...

Page 65: ...series It can be used in all 75XL CPUs including those having a ROM of 16KB or more Table 4 1 shows the differences between Mk I mode and Mk II mode Table 4 1 Differences between Mk I Mode and Mk II Mode Mk I mode Mk II mode Number of stack bytes in a subroutine instruction 2 bytes 3 bytes BRA addr1 instruction Undefined operation Normal operation CALLA addr1 instruction CALL addr instruction 3 ma...

Page 66: ...t the beginning of the program To use the CPU in Mk II mode initialize it to 00xxBNote Figure 4 1 Stack Bank Selection Register Format Note Specify the desired value in xx Caution The CPU operates in Mk I mode after the RESET signal is issued because bit 3 of SBS is set to 1 Set bit 3 of SBS to 0 Mk II mode to use the CPU in Mk II mode SBS0 SBS1 SBS2 SBS3 0 1 2 3 F84H Address SBS Symbol 0 0 0 1 Me...

Page 67: ...instruction When a branch instruction BR BRA BRCB is executed immediate data indicating the branch destination and the contents of a register pair are set in all or some bits of the program counter When a subroutine call instruction CALL CALLA CALLF is executed or a vectored interrupt occurs the current contents of the program counter already incremented return address for fetching the next instru...

Page 68: ...ction BR addr allows a branch to addresses contents of the PC less 15 to one or plus two to 16 regardless of block The program memory is located at following addresses 0000H to 0FFFH µPD750004 0000H to 17FFH µPD750006 0000H to 1FFFH µPD750008 0000H to 3FFFH µPD75P0016 The following addresses are assigned to special functions All areas excluding 0000H and 0001H can be used as normal program memory ...

Page 69: ...nch address specified in BR addr instruction 15 to 1 2 to 16 Entry address specified in CALLF faddr instruc tion Branch address specified in BRCB caddr instruc tion MBE RBE 000CH 0FFFH 0800H 07FFH Internal reset start address Internal reset start address INTBT INT4 start address INTBT INT4 start address INT0 start address INT0 start address INT1 start address INT1 start address INTCSI start addres...

Page 70: ...truction 15 to 1 2 to 16 Entry address specified in CALLF faddr instruc tion Branch address specified in BRCB caddr instruc tion MBE RBE 000CH 17FFH 0800H 07FFH Internal reset start address Internal reset start address INTBT INT4 start address INTBT INT4 start address INT0 start address INT0 start address INT1 start address INT1 start address INTCSI start address INTCSI start address INTT0 start a...

Page 71: ...r instruction 15 to 1 2 to 16 Entry address specified in CALLF faddr instruc tion Branch address specified in BRCB caddr instruc tion MBE RBE 000CH 1FFFH 0800H 07FFH Internal reset start address Internal reset start address INTBT INT4 start address INTBT INT4 start address INT0 start address INT0 start address INT1 start address INT1 start address INTCSI start address INTCSI start address INTT0 st...

Page 72: ...addr instruc tion Branch address specified in BRCB caddr instruc tion MBE RBE 000CH 3FFFH 0800H 07FFH Internal reset start address Internal reset start address INTBT INT4 start address INTBT INT4 start address INT0 start address INT0 start address INT1 start address INT1 start address INTCSI start address INTCSI start address INTT0 start address INTT0 start address INTT1 start address INTT1 start ...

Page 73: ...ss However the memory can be manipulated in 8 bit units using an 8 bit memory manipulation instruction and in bit units using a bit manipulation instruction Note that an even address must be specified in an 8 bit manipulation instruction Note Memory bank 0 or 1 can be selected as the stack area General register area The general register area can be manipulated with either general register manipula...

Page 74: ...te data or a register pair For details on the selection of a memory bank and addressing see Section 3 1 For how to use the particular data memory areas see the following sections and chapter General register area Section 4 5 Stack memory area Section 4 7 Peripheral hardware area Chapter 5 Figure 4 7 Data Memory Map Note Memory bank 0 or 1 can be selected as the stack area 32 x 4 Data memory 000H 0...

Page 75: ...erwise unexpected bugs may occur Example The following program clears data at addresses 000H to 1FFH in RAM SET1 MBE SEL MB0 MOV XA 00H MOV HL 04H RAMC0 MOV HL A Clear 04H to FFHNote INCS L L L 1 BR RAMC0 INCS H H H 1 BR RAMC0 SEL MB1 RAMC1 MOV HL A Clear 100H to 1FFH INCS L L L 1 BR RAMC1 INCS H H H 1 Note Data memory locations at 000H to 003H are allocated to general registers XA and HL so these...

Page 76: ...hese three register pairs can be used as data pointers In 8 bit manipulation the register pairs in the register banks 0 1 2 3 that have the inverted value of bit 0 of the register bank RB address can be specified as BC DE HL and XA in addition to the register pairs BC DE HL and XA See Section 3 2 A general register area can be addressed and accessed as normal RAM regardless of whether it is used a...

Page 77: ...A register is mainly used for 4 bit data processing instructions and the XA register pair is mainly used for 8 bit data processing instructions For a bit manipulation instruction the carry flag CY functions as a bit accumulator Figure 4 10 Accumulator 0 3 C 0 3 B 0 3 E 0 3 D 0 3 L 0 3 H 0 3 A 0 3 X One bank Bit accumulator 4 bit accumulator 8 bit accumulator CY A A X ...

Page 78: ... 4 12 to 4 15 show data saved to and restored from stack memory in these stack operations To place the stack area at a given location the SP can be initialized with an 8 bit memory manipulation instruction and the SBS can be initialized with a 4 bit memory manipulation instruction Both can be read from as well When the SP is initialized to 00H a stack operation starts at the high order address nFF...

Page 79: ...ck area MOV XA 00H MOV SP XA SP 00H Figure 4 12 Data Saved to the Stack Memory Mk I Mode Note PC12 and PC13 are 0 in the µPD750004 PC13 is 0 in the µPD750006 and µPD750008 SP SP SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 SBS0 SBS1 0 SBS3 SP SBS Symbol F80H F84H Address SBS 0FFH 100H 000H 1FFH Memory bank 0 Memory bank 1 Note SP 6 PC11 PC8 MBE SP 4 PC3 PC0 PC7 PC4 SP 2 IST1 CY SP 5 SP 3 SP 1 Stack RBE PC12 IST0...

Page 80: ... 1 SP PC11 PC8 PC3 PC0 PC7 PC4 Stack CALL CALLA or CALLF instruction SP 6 SP 5 SP 4 SP 3 SP 2 SP 1 SP MBE RBE 0 0 PC11 PC8 PC3 PC0 PC7 PC4 Stack Interrupt SP 6 SP 5 SP 4 SP 3 SP 2 SP 1 SP IST1 CY IST0 SK2 MBE SK1 RBE SK0 PSW 0 0 Note 2 PC12 PC12 PC13 PC13 Note 1 Note 1 Note 1 Note 1 Figure 4 13 Data Restored from the Stack Memory Mk I Mode Note PC12 and PC13 are 0 in the µPD750004 PC13 is 0 in the...

Page 81: ...ot saved or restored Remark indicates an undefined bit Lower bits of pair register Upper bits of pair register Stack POP instruction SP SP 1 SP 2 PC11 PC8 PC3 PC0 PC7 PC4 Stack RET or RETS instruction SP SP 1 SP 2 SP 3 SP 4 SP 5 SP 6 MBE RBE 0 0 PC11 PC8 PC3 PC0 PC7 PC4 Stack RETI instruction IST1 CY IST0 SK2 MBE SK1 RBE SK0 PSW 0 0 Note 2 SP SP 1 SP 2 SP 3 SP 4 SP 5 SP 6 PC12 PC12 PC13 Note 1 PC1...

Page 82: ... is executed MBE and RBE are restored When a RETI is executed All PSW bits are restored 1 Carry flag CY The carry flag is a 1 bit flag used to store information about an overflow or underflow that occurs when an arithmetic operation with a carry ADDC SUBC is executed The carry flag functions as a bit accumulator and therefore can be used to store the result of a Boolean algebra operation performed...

Page 83: ...aves CY and all other PSW bits to stack memory in parallel RETI Restores CY together with the other PSW bits from stack memory in parallel Remark mem bit represents the following bit addressing fmem bit pmem L H mem bit Example Bit 3 at address 3FH is ANDed with P33 then the result is set in P50 MOV H 3H Set the high order 4 bits of the address in H register MOV1 CY H 0FH 3 CY bit 3 at 3FH AND1 CY...

Page 84: ...on after manipulating this flag 4 Memory bank enable flag MBE The memory bank enable flag is a 1 bit flag used to specify the address information generation mode for the high order four bits of a 12 bit data memory address The MBE can be set or reset any time with a bit manipulation instruction regardless of memory bank setting When the MBE is set to 1 the data memory address space is expanded all...

Page 85: ...Bn instruction and SEL MBn instruction respectively The contents of the BS can be saved to or restored from a stack memory eight bits at a time by using the PUSH BS POP BS instruction Figure 4 17 Bank Select Register Format 1 Memory bank select register MBS The memory bank select register is a 4 bit register used to store the high order four bits of a 12 bit data memory address The contents of thi...

Page 86: ...6 Register Bank to Be Selected with the RBE and RBS Bank 0 is always selected RBE RBS 3 2 1 0 0 0 0 x x Bank 0 is selected 0 0 Bank 1 is selected 1 0 0 0 1 Bank 2 is selected 1 0 Bank 3 is selected 1 1 Register bank x Don t care Always 0 ...

Page 87: ... bit units so that these ports can be controlled in various ways Example 1 To test the condition of P13 and output different values to ports 4 and 5 according to the test result SKT PORT1 3 Skips if bit 3 of port 1 is 1 MOV XA 18H XA 18H String effect instructions MOV XA 14H XA 14H SEL MB15 Or CLR1 MBE OUT PORT4 XA Port 5 4 XA 2 SET1 PORT4 L Sets the bit s specified by the L register in ports 4 to...

Page 88: ... specified bit by bit with a can withstand paired allowing data I O in units of mask optionNote 3 13V 8 bits PORT8 2 bit I O Allows input or output mode setting in units of 2 bits Notes 1 Can directly drive the LED 2 Only for the µPD75P0016 3 The µPD75P0016 does not have a mask option and cannot be connected with a pull up resistor P10 is also used as an external vectored interrupt input pin This ...

Page 89: ... VDD Pull up resistor P ch P00 INT4 P01 SCK P02 SO SB0 P03 SI SB1 Bit 0 of POGA Input buffer Output buffer which can be switched to either push pull output or N ch open drain output Pull up resistor VDD P ch P10 INT0 P11 INT1 P12 INT2 P13 TI0 Bit 1 of POGA Input buffer Φ or fX 64 Input buffer with hysteresis TI0 INT2 INT1 INT0 Noise eliminator Selector N ch open drain ...

Page 90: ...s 2 and 7 Note For port 7 only M P X Input buffer PMm 0 Key interruptNote Output latch PMm Bits 2 and 7 of port mode register group B m 2 7 Output buffer Internal bus Pm0 Pm1 Pm2 Pm3 Bit m of POGA Pull up resistor VDD P ch Input buffer with hysteresisNote PMm 1 ...

Page 91: ... 3n and 6n n 0 to 3 Note For port 6n only Bit m of POGA Pull up resistor P ch VDD Pmn Input buffer M P X PMmn 0 PMmn 1 PMmn Output latch Corresponding bits of port mode register group A Output buffer m 3 6 n 0 to 3 Internal bus Input buffer with hysteresisNote Key interruptNote ...

Page 92: ...ure 5 5 Configurations of Ports 4 and 5 Internal bus Input buffer MPX VDD Pm0 Pm1 Pm2 Pm3 PMm 0 PMm 1 PMm Output latch Pull up resistor N ch open drain output buffer Corresponding bits of port mode register group B m 4 5 Mask option ...

Page 93: ... HARDWARE FUNCTIONS Figure 5 6 Configuration of Port 8 Internal bus P80 P81 Bit 0 of POGB Pull up resistor VDD P ch PM8 Ouput latch M P X Output buffer Corresponding bit of port mode register group C Input buffer PM8 1 PM8 0 ...

Page 94: ...ister is set to 0 and functions as an output port when the same corresponding bit is set to 1 When the output mode is selected by the port mode register the contents of the output latch appear on the output pins and so the contents of the output latch must be changed to a desired value before the output mode is set An 8 bit memory manipulation instruction is used to set port mode register group A ...

Page 95: ...ification P32 I O specification P33 I O specification P60 I O specification P61 I O specification P62 I O specification P63 I O specification PM7 PM5 PM4 PM2 7 6 5 4 3 1 2 0 FECH Address PMGB Symbol Port 2 P20 P23 I O specification Port 4 P40 P43 I O specification Port 5 P50 P53 I O specification Port 7 P70 P73 I O specification Port mode register group A Port mode register group B PM8 7 6 5 4 3 1...

Page 96: ...gs Example P50 is ORed with P41 then the result is output to P61 SET1 CY CY 1 AND1 CY PORT5 0 CY CY P50 OR1 CY PORT4 1 CY CY P41 SKT CY BR CLRP SET1 PORT6 1 P61 1 CLRP CLR1 PORT6 1 P61 0 2 4 bit manipulation instructions All 4 bit memory manipulation instructions including the IN OUT MOV XCH ADDS and INCS instructions can be used However before these instructions can be executed memory bank 15 mus...

Page 97: ...an be used for ports 4 and 5 that allow 8 bit manipulation As with 4 bit manipulation memory bank 15 must be selected in advance Example The data contained in the BC register pair is output on the output port specified by 8 bit data applied to ports 4 and 5 SET1 MBE SEL MB15 IN XA PORT4 XA ports 5 4 MOV HL XA HL XA MOV XA BC XA BC MOV HL XA Port L XA ...

Page 98: ...2 CLR1 PORTn bit CLR1 PORTn L Note 2 SKT PORTn bit SKT PORTn L Note 2 SKF PORTn bit SKF PORTn L Note 2 MOV1 CY PORTn bit MOV1 CY PORTn LNote 2 MOV1 PORTn bit CY MOV1 PORTn L CY Note 2 AND1 CY PORTn bit AND1 CY PORTn LNote 2 OR1 CY PORTn bit OR1 CY PORTn LNote 2 XOR1 CY PORTn bit XOR1 CY PORTn LNote 2 Notes 1 MBE 0 or MBE 1 MBS 15 must be set before execution 2 The low order two bits of an address ...

Page 99: ...the accumulator is latched in the output latch with the output buffers kept off When the INCS instruction is executed the 4 bit data existing on the pins plus 1 is latched in the output latch with the output buffers kept off When an instruction such as the SET1 CLR1 or SKTCLR instruction is executed to rewrite a data memory bit the output latch data of the specified bit can be rewritten according ...

Page 100: ... A HL SKE A HL Pin data is compared with the Output latch data is com SKE XA HL accumulator pared with the accumulator OUT PORTn A Accumulator data is transferred to the Accumulator data is transferred to the OUT PORTn XA output latch with the output buffers kept output latch and is output on the pins MOV HL A off MOV HL XA XCH A PORTn Pin data is transferred to the accumulator Data is exchanged b...

Page 101: ...in Pull Up Resistors Port pin name Pull up resistor incorporation specification method Bit of POGA Bit of POGB Port 0 P01 P03 Note Connection specification by software in 3 bit units Bit 0 Port 1 P10 P13 Connection specification by software in 4 bit units Bit 1 Port 2 P20 P23 Bit 2 Port 3 P30 P33 Bit 3 Port 6 P60 P63 Bit 6 Port 7 P70 P73 Bit 7 Port 4 P40 P43 Incorporation specification by mask opt...

Page 102: ...timing chart when a built in pull up resistor is connected to a port pin by software Figure 5 9 I O Timing Chart of Digital I O Ports 1 2 a When data is input by a 1 machine cycle instruction PO7 PO6 PO3 PO1 PO2 PO0 7 6 5 4 3 1 2 0 FDCH Address POGA Symbol Port 0 P01 P03 Port 1 P10 P13 Port 2 P20 P23 Port 3 P30 P33 Port 6 P60 P63 Port 7 P70 P73 0 1 Built in pull up resistor not connected Built in ...

Page 103: ...nstruction Figure 5 10 ON Timing Chart of Built in Pull Up Resistor Connected by Software Instruction execution 2 machine cycles Input timing Manipulation instruction Instruction execution Pull up resistor specification register 2 machine cycles Built in pull up resistor setting instruction Instruction execution Manipulation instruction Output latch output pin 3 0 1 Φ Φ Φ Instruction execution Out...

Page 104: ... One clock cycle tCY of the CPU clock F is equal to one machine cycle of an instruction Subsystem clock generator Main system clock generator Clock timer Basic interval timer BT Timer event counter Timer counter Serial interface Clock timer INT0 noise eliminator Clock output circuit 1 1 to 1 4096 Frequency divider Selec tor Selec tor Frequency divider Φ Oscillator disable signal Internal bus HALTN...

Page 105: ...C can be set to select the subsystem clock for very low speed low current operation 122 µs at 32 768 kHz The value in the PCC does not affect the CPU clock e When the subsystem clock is selected main system clock generation can be stopped with the SCC In addition the HALT mode can be used but the STOP mode cannot be used Subsystem clock generation cannot be stopped f The clock to be supplied to pe...

Page 106: ... the STOP instruction and HALT instruction respectively The STOP instruction and HALT instruction can always be executed regardless of MBE setting The CPU clock can be selected only while the processor is operated by the main system clock When the processor is operated by the subsystem clock the low order 2 bits of the PCC are invalidated and fXT 4 is automatically set The STOP instruction can be ...

Page 107: ... 8 750 kHz Φ fX 4 1 5 MHz 1 33 µs 0 67 µs 122 µs 0 0 1 0 0 1 1 1 Operation with f X 4 19 MHz is actual frequency at fX 4 19 MHz CPU clock frequency Φ fX 64 65 5 kHz 1 machine cycle 1 machine cycle SCC3 SCC0 00 is actual frequency at fXT 32 768 kHz SCC3 SCC0 01 or 11 CPU clock frequency Φ fXT 4 8 192 kHz Φ fX 16 262 kHz Φ fX 8 524 kHz Φ fX 4 1 05 MHz 1 91 µs 15 3 µs 122 µs 0 0 1 0 0 1 1 1 Normal op...

Page 108: ... system clock This means that to terminate main system clock generation bit 3 of the SCC must be set to 1 when the machine cycles indicated in Table 5 4 or more have elapsed after the clock is switched from the main system clock to the subsystem clock 2 When the main system clock is used for operation setting bit 3 of the SCC to stop clock generation does not enter the normal STOP mode 3 When the ...

Page 109: ...tested by bit 3 of the clock mode register WM Figure 5 15 External Circuit for the Subsystem Clock Oscillator a Crystal oscillation b External clock Cautions 1 When the external clock is used as the main system clock or subsystem clock the STOP mode cannot be set This is because the X1 pin is connected to VSS in the STOP mode 2 When the main system clock or subsystem clock oscillator is used confo...

Page 110: ...o minimize current con sumption For this reason more malfunctions can occur due to noise than the main system clock oscillator So pay special attention to wiring when using the subsystem clock Figure 5 16 gives examples of oscillator connections which should be avoided Figure 5 16 Examples of Oscillator Connections Which Should Be Avoided 1 2 a The wiring is too long b The signal lines cross Remar...

Page 111: ... and C fluctuates e A signal is taken directly from f The signal lines of the main system the resonator clock and subsystem clock are parallel and adjacent to each other Remark When wiring the subsystem clock read X1 and X2 as XT1 and XT2 respectively In this case a resistor must be added to XT2 in series µPD750008 VSS X1 X2 High current µPD750008 VSS XT1 XT2 X1 X2 XT2 and XT1 are wired in paralle...

Page 112: ...ctions to decrease the supply current The function to select with the software whether to use the built in feedback resistor The function to suppress the supply current by reducing the drive current of the built in inverter when the operating supply voltage is high VDD 2 7 V Each function can be used by switching bits 0 and 1 in the sub oscillator control register SOS See Figure 5 17 Figure 5 17 S...

Page 113: ...h flag The built in inverter in the subsystem clock oscillator of the µPD750008 subseries has a large drive current because it can be used at low supply voltage VDD 1 8 V so that the supply current becomes too high to use at high supply voltage VDD 2 7 V To reduce the supply current set SOS 1 to 1 so as to reduce the drive current of the inverter However if SOS 1 is set to 1 when VDD is less than ...

Page 114: ... so other than 0001B is set When the system operates on the subsystem clock the PCC must also be other than 0001B 2 The fluctuation of the ambient temperature around an oscillator and the performance of a load capacity change fX and fXT In particular when fX is higher than the nominal value or fXT is lower than the nominalvalue the machine cycles calculated by fX 64fXT fX 8fXT and fX 4fXT in Table...

Page 115: ... clock In this case subsystem clock generation must have been started After a time 46 machine cycles required to switch to the subsystem clock elapses bit 3 of the SCC is set to 1 to terminate main system clock generation 4 After detecting the input of commercial current by using an interrupt bit 3 of the SCC is cleared to start main system clock generation After a time required for stable generat...

Page 116: ...outputting a clock pulse signal is as follows a Select a clock output frequency and disable clock output b Write a 0 in the P22 output latch c Set the output mode for port 2 d Enable clock output Figure 5 20 Configuration of the Clock Output Circuit Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output From the clock genera...

Page 117: ...utput Figure 5 21 Format of the Clock Output Mode Register Caution Be sure to write a 0 in bit 2 of the CLOM Address FD0H 3 2 1 0 CLOM0 Symbol CLOM Φ outputNote 1 05 MHz 524 kHz 262 kHz 65 5 kHz fX 23 output 524 kHz fX 24 output 262 kHz 0 0 1 0 0 1 1 1 CLOM1 0 CLOM3 fX 2 6 output 65 5 kHz fX 4 19 MHz Note Φ is the CPU clock selected by PCC 0 1 Output disable Output enable Clock output enable disab...

Page 118: ...ntrol output is selected by the clock frequency select bit of the clock output mode register Pulse output is enabled or disabled by controlling the clock output enable disable bit by software The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output Figure 5 22 Application to Remote Control Output PCL pin output Bit 3 of CLOM ...

Page 119: ...am of the Basic Interval Timer Watchdog Timer Note Instruction execution 5 3 2 Basic Interval Timer Mode Register BTM The BTM is a 4 bit register for controlling operation of the basic interval timer BT A 4 bit memory manipulation instruction is used to set the BTM Bit 3 can be independently manipulated using a bit manipulation instruction Example The interrupt generation interval is set to 1 37 m...

Page 120: ...the basic interval timer watchdog timer operation starts the counter and the interrupt request flag are cleared When the operation starts this bit is automatically reset to 0 Basic interval timer watchdog timer start control bit Interrupt interval time wait time for releasing standby fX 212 1 02 kHz fX 2 9 8 18 kHz fX 27 32 768 kHz fX 25 131 kHz 220 fX 250 ms 217 fX 31 3 ms 2 15 fX 7 82 ms 2 13 fX...

Page 121: ...d by the clock supplied from the clock generator So it is impossible to stop the timer from incrementing One of four interrupt generation intervals can be selected by setting BTM See Figure 5 24 BT and IRQBT can be cleared by setting bit 3 of BTM to 1 instruction for starting as an interval timer The count status of BT can be read by an 8 bit manipulation instruction No data can be loaded to the t...

Page 122: ...oes not reach the instruction which clears BT within the set interval in which case a program error leading to a program crash may have occurred BT overflows and an internal reset signal is generated to forcibly terminate the program The occurrence of internal reset possibly means that a program crash has occurred A crash can thus be detected Set the watchdog timer as follows 1 and 2 can be perfor...

Page 123: ...leased To allow the system clock to stabilize after releasing the STOP mode a wait function is available which stops the operation of the CPU until the basic interval timer BT overflows The wait time after generation of a RESET signal is fixed as specified by a mask option On the other hand a wait time can be selected by setting BTM when releasing the STOP mode with an interrupt occurrence In this...

Page 124: ...Read the count value of BT SET1 MBE SEL MB15 MOV HL BT Set the BT address in HL LOOP MOV XA HL First read MOV BC XA MOV XA HL Second read SKE XA BC BR LOOP 2 Set the high level width of pulses applied to the INT4 interrupt pin both edges detected The pulse width is assumed not to exceed the value 5 46 ms or longer at 6 00 MHz set in the BTM INT4 interrupt routine MBE 0 LOOP MOV XA BT First read MO...

Page 125: ...ther the main system clock or the subsystem clock can be used to produce 0 5 second intervals Use a main system clock of 4 194304 MHz c The fast forward mode produces an interval 128 times faster 3 91 ms which is useful for program debugging and testing d Any of the frequencies 2 048 kHz 4 096 kHz and 32 768 kHz can be output to the P23 BUZ pin so that it can be used for sounding the buzzer and fo...

Page 126: ...led by an 8 bit manipulation instruction Bit 3 is for testing the XT1 pin input level The input level of the XT1 pin can be tested by bit test operation No data can be written to this register When the RESET signal is generated all bits except bit 3 of this register are cleared to 0 P23 BUZ Internal bus 8 Selector From the clock generator fX 128 32 768 kHz fXT 32 768 kHz Selector Frequency divider...

Page 127: ...t WM1 0 1 Normal clock mode sets IRQW at 0 5 seconds Advanced clock mode sets IRQW at 3 91 ms Operation mode selection bit WM2 0 1 Disables clock operation clears the frequency dividing circuit Enables clock operation Clock operation enable disable bit WM3 0 1 Input to the XT1 pin is low level Input to the XT1 pin is high level XT1 pin input level bit test only WM5 WM4 0 BUZ output frequency 2 048...

Page 128: ...er counter The timer event counter has the following functions a Programmable interval timer operation b Square wave output of any frequency to the PTOn pin c Event counter operation Channel 0 only d Divides the frequency of signal input via the TI0 pin to 1 Nth of the original signal and outputs the divided frequency to the PTO0 pin frequency divider operation Channel 0 only e Supplies the serial...

Page 129: ...om the clock generator Internal bus TM06 TM05 TM04 TM03 TM02 Port input buffer Comparator 8 Modulo register 8 TO enable flag P20 output latch signal Port 2 input output mode Clear signal T0 TMOD0 Bit 2 of PMGB P20 PTO0 Output buffer Reset RESET IRQT0 clear signal TOUT flip flop TM0 Input buffer IRQT0 set signal INTT0 PORT2 0 TOE0 To serial interface CP Match 8 8 TOUT0 ...

Page 130: ... signal 8 8 8 From the clock generator Internal bus TM16 TM15 TM14 TM13 TM12 Comparator 8 Modulo register 8 TO enable flag P21 output latch signal Port 2 input output mode Clear signal T1 TMOD1 Bit 2 of PMGB P21 PTO1 Output buffer Reset RESET IRQT1 clear signal TOUT flip flop TM1 IRQT1 set signal INTT1 PORT2 1 TOE1 CP Match 8 8 ...

Page 131: ...on Bit 3 is a timer start bit and can be operated bit wise It is automatically reset to 0 when the timer operation starts All the bits of the timer event counter mode register are cleared to 0 by a RESET signal generation Examples 1 Start the timer in the interval timer mode of CP 5 86 kHz during 6 00 MHz operation SEL MB15 or CLR1 MBE MOV XA 01001100B MOV TMn XA TMn 4CH 2 Restart the timer accord...

Page 132: ...6 5 TM05 4 TM04 3 TM03 2 TM02 1 0 Symbol TM0 TM03 Timer start indication bit When 1 is written into the bit the counter and IRQT0 flag are cleared If bit 2 is set to 1 count operation is started TM02 0 1 Operation mode Stop retention of count contents Count operation Count operation Count pulse CP selection bit When fX 6 00 MHz TM05 0 0 0 0 1 1 TM06 0 0 1 1 1 1 TM04 0 1 0 1 0 1 TI0 rising edge TI0...

Page 133: ...s set to 1 count operation is started TM12 0 1 Operation mode Stop retention of count contents Count operation Count operation Other than above Other than above When fX 4 19 MHz TM15 0 0 1 1 TM16 1 1 1 1 TM14 0 1 0 1 fX 212 1 02 kHz fX 210 4 09 kHz fX 28 16 4 kHz fX 26 65 5 kHz Not to be set Count pulse CP Count pulse CP select bit When fX 6 00 MHz TM15 0 0 1 1 TM16 1 1 1 1 TM14 0 1 0 1 fX 212 1 4...

Page 134: ...8 bit programmable interval timer and event counter operation channel 0 only 1 Register setting The following three registers and one flag are used in the 8 bit timer event counter mode Timer event counter mode register TMn Timer event counter count register Tn Timer event counter modulo register TMODn Timer event counter output enable flag TOEn a Timer event counter mode register TMn When the 8 b...

Page 135: ... and IRQT0 flag are cleared If bit 2 is set to 1 count operation is started TM03 TM02 Operation mode Count operation 0 1 Stop retention of count contents Count operation 7 6 TM06 5 TM05 4 TM04 3 TM03 2 TM02 1 0 Address FA0H Symbol TM0 Count pulse CP selection bit TI0 rising edge TI0 falling edge fX 210 fX 28 fX 26 fX 24 Not to be set TM05 0 0 0 0 1 1 TM06 0 0 1 1 1 1 TM04 0 1 0 1 0 1 Count pulse C...

Page 136: ...on bit When 1 is written to the bit the counter and IRQT1 flag are cleared If bit 2 is set to 1 count operation is started TM13 TM12 Operation mode Count operation Other than above 0 1 Stop retention of count contents Count operation 7 6 TM16 5 TM15 4 TM14 3 TM13 2 TM12 1 0 Address FA8H Symbol TM1 Count pulse CP selection bit fX 212 fX 210 fX 28 fX 26 Not to be set TM15 0 0 1 1 TM16 1 1 1 1 TM14 0...

Page 137: ...s set in the modulo register for each count pulse to the timer event counter Table 5 6 Resolution and Longest Setup Time a When timer event counter channel 0 Mode register At 6 00 MHz At 4 19 MHz TM06 TM05 TM04 Resolution Longest setup time Resolution Longest setup time 1 0 0 171 µs 43 7 ms 244 µs 62 5 ms 1 0 1 42 7 µs 10 9 ms 61 0 µs 15 6 ms 1 1 0 10 7 µs 2 73 ms 15 3 µs 3 91 ms 1 1 1 2 67 µs 683...

Page 138: ...ormally begins operation in the following procedure 1 Set a count in the TMODn 2 Set the operating mode count pulse and start indication in the TMn Caution Set a value other than 00H in the modulo register TMODn When using the timer event counter output pin PTOn set the dual function pin P2n as follows 1 Clear the output latch of P2n 2 Set port 2 to the output mode 3 Make a status wherein the inte...

Page 139: ...am SEL MB15 MOV XA 0AEH MOV TMOD0 XA Set the modulo register MOV XA 01001100B MOV TM0 XA Set the mode register and start the timer EI Enable an interrupt EI IET0 Enable a timer interrupt Remark In this application the TI0 pin can be used as an input pin b An interrupt is caused when the number of pulses active high applied to the TI0 pin reaches 100 The high order four bits of the mode register ar...

Page 140: ...ed bit 3 of the TM0 is set the count register T0 and the interrupt request flag IRQT0 are cleared However when the timer is placed in the operation mode and the setting of IRQT0 and the start of the timer occur at the same time IRQT0 may not be cleared This causes no problem if IRQT0 is used for a vectored interrupt However if IRQT0 is being tested a problem arises because IRQT0 is set even if the...

Page 141: ...the count register are held by a read instruction for one machine cycle so that a signal applied to the TI0 pin must have a pulse wider than that 4 Notes on changing the count pulse When the count pulse is changed by rewriting the contents of the timer event counter mode register this takes effect immediately after the rewrite instruction is executed A combination of clocks used for changing count...

Page 142: ...ration until it overflows then it restarts count operation from 0 Accordingly if the new value m of the modulo register is less than the value n before it is changed the timer must be restarted after the contents of the modulo register are changed Re set instruction Re set instruction Clock A specified Clock B specified Clock A specified Clock A Clock B CP 1 2 n m x 1 x 255 0 1 n x m Modulo regist...

Page 143: ...erred through two lines Serial clock SCK and serial data bus SB0 or SB1 By controlling output levels on the two lines by software communication with multiple devices is enabled The output levels of SCK and SB0 or SB1 can be controlled by software so the user can match an arbitrary transfer format This means that a line that has been required for handshaking to connect multiple lines can be elimina...

Page 144: ...e SBI System Configuration 5 6 2 Configuration of Serial Interface Figure 5 39 shows the block diagram of the serial interface SCK Master CPU SB0 SB1 SCK SB0 SB1 Slave CPU 1 Address 1 SCK SB0 SB1 Slave IC N Address N Address Command Data Serial clock VDD ...

Page 145: ...CKD ACKT ACKE BSYE RELT CMDT D Q SET CLR 8 8 SBIC Bit test Slave address register SVA Address comparator Match signal Bit manipulation SO latch Bit test Selec tor Selec tor Busy acknowledge output circuit Bus release command acknowledge detection circuit Serial clock counter Serial clock control circuit INTCSI control circuit IRQCSI set signal INTCSI P01 output latch Serial clock selector External...

Page 146: ...ck counter counts the serial clock to be output or input during transfer and checks whether 8 bit data has been transferred 7 Slave address register SVA and address comparator In the SBI mode SVA is used when the µPD750008 is used as a slave device A slave sets the number assigned to it slave address in SVA The master outputs a slave address to select a particular slave Two data values a slave add...

Page 147: ...t latch to 1 5 6 3 Register Functions 1 Serial operation mode register CSIM Figure 5 40 shows the format of serial operation mode register CSIM CSIM is an 8 bit register which specifies a serial interface operation mode serial clock wake up function and so forth CSIM is manipulated using an 8 bit memory manipulation instruction The higher three bits can be manipulated bit by bit Each bit can be ma...

Page 148: ... shift in the shift register register Note COI can be read only before serial transfer is started or after serial transfer is completed An undefined value may result during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W WUP 0 Sets IRQCSI each time serial transfer is completed in each mode 1 Used in the SBI mode only to set IRQCSI only...

Page 149: ...ire SIO7 0 XA SB0 P02 P03 input serial Transfer starting N ch open drain I O I O mode with MSB 1 P02 input SB1 P03 N ch open drain I O Remark x Don t care Serial clock selection bit W CSIM1 CSIM0 Serial clock SCK pin mode 3 wire serial I O mode SBI mode 2 wire serial I O mode 0 0 Input clock externally applied to SCK pin Input 0 1 Timer event counter output TOUT0 Output 1 0 fX 24 375 kHz at 6 00 M...

Page 150: ...When clearing CSIE during serial transfer use the following procedure 1 Disable interrupts by clearing the interrupt enable flag IECSI 2 Clear CSIE 3 Clear the interrupt request flag IRQCSI Examples 1 fX 24 is selected as the serial clock serial interrupt IRQCSI is generated each time serial transfer is completed and serial transfer is performed in the SBI mode with the SB0 pin used as the serial ...

Page 151: ...may not allow read and or write operation Figure 5 41 When the RESET signal is generated all bits are cleared to 0 Caution Only the following bits can be used in the three wire and two wire serial I O modes Bus release trigger bit RELT Sets the SO latch Command trigger bit CMDT Clears the SO latch Figure 5 41 Format of Serial Bus Interface Control Register SBIC 1 3 Remarks 1 R Read only 2 W Write ...

Page 152: ... enable bit R W ACKE 0 Disables automatic output of the acknowledge signal ACK Output by ACKT is possible 1 When set before transfer ACK is output in phase with the 9th clock of SCK When set after transfer ACK is output in phase with SCK immediately following the set instruction execution Acknowledge trigger bit W ACKT When set after transfer ACK is output in phase with the next SCK After ACK sign...

Page 153: ...clear SB0 or SB1 during serial transfer Be sure to clear SB0 or SB1 before or after serial transfer Bus release trigger bit W RELT Control bit for bus release signal REL trigger output By setting RELT 1 the SO latch is set to 1 Then the RELT bit is automatically cleared to 0 Caution Never clear SB0 or SB1 during serial transfer Be sure to clear SB0 or SB1 before or after serial transfer Examples 1...

Page 154: ... start of serial transfer writing to SIO is as follows When the serial interface operation enable disable bit CSIE 1 However the case where CSIE is set to 1 after data is written to the shift register is excluded When the serial clock is masked after 8 bit serial transfer SCK is high When reading from or writing to SIO make sure that SCK is high In the two wire serial I O mode and SBI mode the pin...

Page 155: ... when addresses commands or data is transferred with the µPD750008 operating as the master or when data is transferred with the µPD750008 operating as a slave For details see 6 in Section 5 6 6 and 8 in Section 5 6 7 5 6 4 Operation Halt Mode The operation halt mode is used when serial transfer is not performed This mode reduces power consumption The shift register does not perform shift operation...

Page 156: ...g to the setting of CSIM0 and CSIM1 CSIM1 CSIM0 P01 SCK pin state 0 0 High impedance 0 1 High level output 1 0 1 1 When clearing CSIE during serial transfer use the following procedure 1 Disable interrupts by clearing the interrupt enable flag IECSI 2 Clear CSIE 3 Clear the interrupt request flag IRQCSI CSIE COI WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0 FE0H CSIM 7 6 5 4 3 2 1 0 Address Serial clock selec...

Page 157: ...erial operation mode register CSIM To use the three wire serial I O mode set CSIM as shown below For details on CSIM format see 1 in Section 5 6 3 CSIM0 is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIM can be manipulated bit by bit When the RESET signal is input CSIM is set to 00H In the figure below hatched portions indicate the bits used in the three wire serial I O ...

Page 158: ...nly before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W WUP 0 Sets IRQCSI each time serial transfer is completed Serial interface operation mode selection bit W CSIM4 CSIM3 CSIM2 Shift register sequence SO pin function SI pin funct...

Page 159: ...tting RELT 1 the SO latch is set to 1 Then the RELT bit automatically cleared to 0 Caution Never use bits other than RELT and CMDT in the three wire serial I O mode 2 Communication operation The three wire serial I O mode transfers data with eight bits as one block Data is transferred bit by bit in phase with the serial clock The shift register performs shift operation on the falling edge of the s...

Page 160: ...e P01 output latch in the output mode internal system clock mode See Section 5 6 8 3 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation mode register 0 CSIM The serial clock can be selected out of the following four clocks Table 5 7 Serial Clock Selection and Application In the Three Wire Serial I O Mode Mode register Serial clock Timing for shift registe...

Page 161: ...Figure 5 46 read or write operation can be performed by switching between the MSB and LSB This switching can be specified using bit 2 of serial operation mode register CSIM Figure 5 46 Transfer Bit Switching Circuit The first bit is switched by changing the order of data bits written to shift register SIO The shift operation order of SIO is always the same Accordingly the first bit must be switche...

Page 162: ...d with the HL register to SIO load the SIO data to the accumulator and start serial transfer MOV XA HL Fetch transmit data from RAM SEL MB15 or CLR1 MBE XCH XA SIO Exchange transmit data and receive data and start transfer 7 Application of the three wire serial I O mode a Data is transferred starting with the MSB on a transfer clock of 262 kHz during 4 19 MHz operation Master operation Sample prog...

Page 163: ...A Serial operation halt MSB LSB invert mode external clock MOV XA TDATA MOV SIO XA Set transfer data and start transfer EI IECSI EI Interrupt routine MBE 0 MOV XA TDATA XCH XA SIO Start to transfer receive data and transmit data MOV RDATA XA Save receive data RETI c Data is transmitted and received at high speed by using a transfer clock of 524 kHz during 4 19 MHz operation P01 SCK SI SB1 SCK SO O...

Page 164: ...5 6 6 Two Wire Serial I O Mode The two wire serial I O mode can be made compatible with any communication format by programming In this mode communication is basically performed using two lines Serial clock SCK and serial data input output SB0 or SB1 Figure 5 47 Example of Two Wire Serial I O System Configuration Remark The µPD750008 can also be used as a slave CPU 1 Register setting To set the tw...

Page 165: ...each mode as well as for port 0 Signal from address comparator R COINote Condition for being cleared COI 0 Condition for being set COI 1 When the slave address register SVA When the slave address register SVA does not match the data of the shift register matches the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed An undef...

Page 166: ...rial bus interface control register SBIC To use the two wire serial I O mode set SBIC as shown below For details on SBIC format see 2 in Section 5 6 3 SBIC is manipulated using a bit manipulation instruction When the RESET signal is input SBIC is set to 00H In the figure below the hatched portions indicate the bits used in the two wire serial I O mode Remark W Write only Command trigger bit W CMDT...

Page 167: ...er on the rising edge of SCK When eight bits have been transferred shift register operation automatically terminates setting the interrupt request flag IRQCSI Figure 5 48 Timing of Two Wire Serial I O Mode The SB0 or SB1 pin becomes an N ch open drain I O when specified as the serial data bus so the voltage level on that pin must be pulled up externally The state of the SO latch is output on the S...

Page 168: ...er serial transfer completed 3 When SCK is high 1 0 fX 26 Low speed 1 1 serial transfer 4 Signals Figure 5 49 shows operations of RELT and CMDT Figure 5 49 Operations of RELT and CMDT 5 Transfer start Serial transfer starts by writing transfer data into shift register SIO provided that the following two conditions are satisfied The serial interface operation enable disable specification bit CSIE i...

Page 169: ...regarded as successful If the result is 0 the occurrence of a transmission error is assumed 7 Application of two wire serial I O mode A serial bus is configured and multiple devices are connected to it Example A system is configured with a µPD750008 as the master to which a µPD75104 µPD75402A and µPD7225G are connected as slaves To configure the bus as shown above connect the SI pin and SO pin The...

Page 170: ...igure a serial bus The master can output on the serial data bus an address for selecting a device subject to serial communication commands directed to the remote device and data A slave can identify an address commands and data from received data by hardware This function simplifies the serial interface control portion of an application program The SBI function is available with devices such as th...

Page 171: ...K and serial data bus SB0 or SB1 For this reason the number of ports on a microcomputer can be reduced and the wiring on a circuit board can be simplified SBI functions are described below a Address command data identification function Serial data is classified into three types Address command and data b Address based chip select function The master selects a chip for a slave by address transfer c...

Page 172: ...nd data Figure 5 51 Timing of SBI Transfer The bus release signal and command signal are output by the master BUSY is output by a slave ACK is output by either the master or a slave Normally the device which received 8 bit data outputs ACK The master continues to output the serial clock from when 8 bit data transfer starts to when BUSY is released SCK A7 SB0 SB1 BUSY 8 9 A0 ACK C7 SB0 SB1 READY 9 ...

Page 173: ...h is output by the master Figure 5 53 Command Signal Slaves contain hardware to detect the command signal c Address An address is 8 bit data and is output by the master to connected slaves to select a particular slave Figure 5 54 Address The 8 bit data following the bus release signal or command signal is defined as an address A slave detects the condition for the addresses by hardware and checks ...

Page 174: ... data without the command signal is defined as data The usage of commands or data can be selected optionally according to the communication specifications e Acknowledge signal ACK The acknowledge signal confirms the reception of serial data between the transmitter and the receiver Master Transmits address for slave 2 Slave 1 Not selected Slave 2 Selected Slave 3 Not selected Slave 4 Not selected S...

Page 175: ...hot pulse output in phase with the falling edge of SCK after 8 bit data transfer This signal may be synchronized with any clock of SCK The transmitter checks if the receiver returns the acknowledge signal after 8 bit data transfer If the acknowledge signal is not returned after a specified period of time the transmitter can assume that the reception failed SCK SB0 SB1 8 9 10 11 ACK SB0 SB1 8 9 ACK...

Page 176: ...sed and a slave enters the state in which the ready signal is to be output 3 Register setting To set the SBI mode manipulate the following two registers Serial operation mode register CSIM Serial bus interface control register SBIC a Serial operation mode register CSIM To use the SBI mode set CSIM as shown below For details on CSIM format see 1 in Section 5 6 3 CSIM is manipulated using an 8 bit m...

Page 177: ...a written by an 8 bit manipulation instruction is ignored Wake up function specification bit W WUP 0 Sets IRQCSI each time serial transfer is completed in each mode 1 Used in the SBI mode only to set IRQCSI only when an address received after bus release matches the data in the slave address register wake up state SB0 or SB1 goes to high impedance state Caution When WUP 1 is set during BUSY signal...

Page 178: ... SBIC is set to 00H In the figure below hatched portions indicate the bits used in the SBI mode Remark R Read only W Write only R W Read write Busy enable bit R W BSYE 0 1 The busy signal is automatically disabled 2 Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction execution 1 The busy signal is output after the acknowledge signal in phase with...

Page 179: ...utions 1 Never set ACKT before or during serial transfer 2 ACKT cannot be cleared by software 3 Before setting ACKT set ACKE 0 Command detection flag R CMDD Condition for being cleared CMDD 0 Condition for being set CMDD 1 1 The transfer start instruction The command signal CMD is detected is executed 2 The bus release signal REL 3 The RESET signal is entered 4 CSIE 0 Figure 5 40 Bus release detec...

Page 180: ...Serial clock Timing for shift register R W and Application CSIM CSIM Source Masking of start of serial transfer 1 0 serial clock 0 0 External Automatically 1 In the operation halt mode Slave CPU SCK masked when CSIE 0 0 1 TOUT 8 bit data 2 When the serial clock is Arbitrary speed flip flop transfer is masked after 8 bit transfer serial transfer completed 3 When SCK is high 1 0 fX 24 Middle speed s...

Page 181: ...DD Master Figure 5 61 Operations of RELT CMDT RELD and CMDD Slave SIO SCK SO latch RELT CMDT RELD CMDD Transfer start request H SIO SCK 1 2 7 8 D7 D6 D1 D0 SO latch RELT Master CMDT Master RELD CMDD Transfer start request Write to SIO When address match is found When address mismatch is found ...

Page 182: ...g the first clock cycle immediately after ACKT is set When set during this period When ACKT is set after transfer completion SCK 1 2 7 8 D7 D6 D2 D1 SB0 SB1 D0 9 ACK ACKE When ACKE 1 at this point The ACK signal is output during the ninth clock cycle SCK 6 7 8 9 D2 D1 D0 SB0 SB1 ACK ACKE The ACK signal is output during the first clock cycle immediately after ACKE is set When ACKE is set during thi...

Page 183: ...period is too short Figure 5 64 Operation of ACKD 1 2 a When ACK signal is output during the ninth SCK clock b When ACK signal is output after the ninth SCK clock SCK SB0 SB1 ACKE The ACK signal is not output When ACKE is set or cleared during this period and ACKE 0 at the falling edge of SCK SIO SCK D2 D1 D0 SB0 SB1 ACKD 9 ACK 8 7 6 Transfer start request Transfer start ...

Page 184: ...transfer is directed during BUSY Figure 5 65 Operation of BSYE SCK SB0 SB1 BSYE 9 BUSY 8 7 6 ACK When BSYE 1 at this point When reset operation is executed during this period and BSYE 0 at the falling edge of SCK SIO SCK D2 D1 D0 SB0 SB1 ACKD 9 BUSY 8 7 6 D7 ACK Transfer start request D6 Transfer start ...

Page 185: ...USY Ready signal READY Output device Definition RELT is set CMDT is set 1 ACKE 1 2 ACKT is set BSYE 1 1 BSYE 0 2 Execution of instruction to write data to SIO Transfer start request Condition for output RELD is set CMDD is clear ed CMDD is set ACKD is set Flag operation Meaning of signal Indicates that CMD signal follows and data transmitted is address data i Data transmitted after REL signal outp...

Page 186: ...struction to write data to SIO when CSIE 1 Serial transfer start request Note 2 Condition for output IRQCSI is set on rising edge of 9th clock of SCK Note 1 Flag operation Meaning of signal Timing of signal output on serial data bus Address of slave device on serial bus Directions and messages to slave device Numeric processed by slave or master device Signal name Timing chart Master Master Master...

Page 187: ...be externally pulled up because it has originally an N ch open drain output Figure 5 66 Pin Configuration Caution When data is received the N ch transistor must be turned off so FFH must be written to SIO beforehand The N ch open drain output can be turned off at any time during transfer However when the wake up function specification bit WUP is set to 1 the N ch transistor is always off so there ...

Page 188: ...methods described below a Comparing SIO data before start of transmission with SIO data after start of transmission With this method the occurrence of a transmission error is assumed if two SIO values disagree with each other b Using the slave address register SVA Transmit data is set in SIO and SVA as well before the data is transmitted On completion of transmission the COI bit match signal from ...

Page 189: ...e operation A6 A5 A4 A3 A2 A1 A0 ACK READY Address Master device processing transmitter Transfer line Slave device processing receiver Interrupt handling preparation for next serial transfer Set ACKD Serial transmission Generate IRQCSI Clear BUSY Serial reception Output BUSY Clear BUSY BUSY Set CMDT Set RELT Set CMDT Write to SIO Stop SCK WUP 0 Set ACKT Set CMDD Clear CMDD Set RELD Set CMDD Genera...

Page 190: ...C7 Hardware operation C6 C5 C4 C3 C2 C1 C0 ACK READY Command Master device processing transmitter Transfer line Slave device processing receiver Interrupt handling preparation for next serial transfer Serial transmission Generate IRQCSI Serial reception Generate IRQCSI Output BUSY Clear BUSY BUSY Set CMDT Write to SIO Set ACKD Stop SCK Read SIO Analyze command Set ACKT Clear BUSY Set CMDD Output A...

Page 191: ...5 6 7 8 9 SB0 or SB1 pin D7 Hardware operation D6 D5 D4 D3 D2 D1 D0 ACK READY Data Master device processing transmitter Transfer line Slave device processing receiver Interrupt handling preparation for next serial transfer Serial transmission Generate IRQCSI Serial reception Generate IRQCSI BUSY Write to SIO Set ACKD Stop SCK Read SIO Set ACKT Clear BUSY Output BUSY Output ACK Clear BUSY ...

Page 192: ...EADY D7 Hardware operation D6 D5 D4 D3 D2 D1 D0 ACK BUSY D7 D6 READY Data Master device processing receiver Transfer line Slave device processing transmitter Write FFH to SIO Read SIO Set ACKT Receive data processing Stop SCK Serial reception Generate IRQCSI Output ACK Serial reception Write to SIO Write to SIO Clear BUSY Serial transmission Generate IRQCSI Set ACKD Output BUSY Clear BUSY Write FF...

Page 193: ... interrupt request flag IRQCSI Example When RAM data specified by the HL register is transferred to SIO from which data is loaded into the accumulator at the same time and serial transfer is started MOV XA HL Extracts transmit data from RAM SEL MB15 or CLR1 MBE XCH XA SIO Exchanges transmit data with receive data and startstransfer 11 Notes on the SBI mode a Whether a slave is selected is determin...

Page 194: ...a Serial bus configuration In the serial bus configuration used for the example of this section a µPD750008 is connected to the bus line as a device on the serial bus Two pins on the µPD750008 are used serial data bus SB0 or SB1 and serial clock SCK P01 Figure 5 71 shows an example of the serial bus configuration Figure 5 71 Example of Serial Bus Configuration SCK SB0 SB1 SCK SB0 SB1 SB0 SB1 SB0 S...

Page 195: ...elected state 2 Commands and data are transferred between the master and the slave selected in 1 Command and data are transferred between the master and the selected slave on a one to one basis so the other slaves must be placed in the non selected state 3 Communication is completed when the selected slave is placed in the non selected state This state is caused in the following cases The selected...

Page 196: ...enough area an error occurs ACK is not returned in this case The master transmits an END command when all data have been transferred The END command informs the slave that all data have been transferred correctly The slave accepts an END command even before data reception is uncompleted In this case the data received just before the acceptance of the END command becomes valid The master compares t...

Page 197: ...s ACK to the current slave STATUS M ACK S Data Status S ACK S Command 7 6 5 4 3 2 1 0 Status MSB LSB All 0s Bit indicating whether there is data ready for transmission 0 No transmit data 1 Transmit data of one byte or more Bit indicating whether the device is ready for data reception 0 No receive data storage area 1 Receive data storage area not smaller than one byte is present Bit indicating whet...

Page 198: ...geable 00H Master not changeable The slave compares the contents of SIO before transfer with the contents of SIO after transfer If the contents of SIO disagree with each other an error occurs ACK is not returned in this case If the master receives 0FFH the master returns ACK to the slave and starts to operate as a slave The slave which transmitted 0FFH starts to operate as the master when it recei...

Page 199: ... transmission the master transmits a STOP command to the slave 5 6 8 Manipulation of SCK Pin Output The SCK P01 pin has a built in output latch so that this pin allows static output by software manipulation in addition to normal serial clock output The number of SCK pulses can be software set arbitrarily by manipulating the P01 output latch The SO SB0 P02 or SI SB1 P03 pin is controlled by manipul...

Page 200: ...CK P01 Pin Circuit Configuration The P01 output latch is mapped to bit 1 of address FF0H A RESET signal sets the P01 output latch to 1 Cautions 1 During normal serial transfer the P01 output latch must be set to 1 2 The P01 output latch cannot be addressed by specifying PORT0 1 as described below The address of the latch 0FF0H 1 must be coded in the operand of an instruction directly However MBE 0...

Page 201: ...the bit to be manipulated can be sequentially shifted for continued processing Figure 5 81 Format of the Bit Sequential Buffer Remarks 1 With pmem L addressing bit specification is shifted according to the L register 2 With pmem L addressing BSB can be manipulated at any time regardless of MBE MBS specification Data can also be manipulated by direct addressing The buffer can be used for applicatio...

Page 202: ...1 MOV BSB0 XA Set BSB0 and BSB1 MOV XA BUFF2 MOV BSB2 XA Set BSB2 and BSB3 MOV L 0 LOOP0 SKT BSB0 L Tests the specification bit of BSB BR LOOP1 NOP Dummy For timing adjustment SET1 PORT3 0 Sets bit 0 of port 3 BR LOOP2 LOOP1 CLR1 PORT3 0 Clears bit 0 of port 3 NOP Dummy For timing adjustment NOP LOOP2 INCS L L L 1 BR LOOP0 RET ...

Page 203: ... interrupt start address can be set arbitrarily c Multiple interrupt function which can specify the priority by the interrupt priority specification register IPS d Test function of an interrupt request flag IRQxxx The software can confirm that an interrupt occurred e Release of the standby mode Interrupts released by an interrupt enable flag can be selected 2 Test functions a Whether test request ...

Page 204: ...detection circuit IM0 Edge detection circuit Edge detection circuit Rising edge detection circuit Falling edge detection circuit KR0 P60 KR7 P73 Selec tor IM2 Interrupt enable flag IExxx IPS IST0 IME Priority control circuit Decoder VRQn Vector table address generator Standby release signal Internal bus Selec tor Note IM1 Note Noise eliminator when the noise eliminator is selected standby mode can...

Page 205: ...INTT1 Match signal between the count In 6 VRQ6 000CH register of timer counter 1 and modulo register Note The interrupt priority is used to determine the priority when two or more interrupts are simultaneously generated Figure 6 2 Interrupt Vector Table MBE RBE INTBT INT4 start address 0002H INTBT INT4 start address MBE RBE INT0 start address 0004H INT0 start address MBE RBE INT1 start address 000...

Page 206: ... processing An assembler pseudo instruction VENTn is used to set a vector table Example A vector table is set for INTBT INT4 VENT1 MBE 0 RBE 0 GOTOBT Vector table at MBE RBE setting value Symbol for indicating address 0002 in interrupt service routine an interrupt service routine start address Caution The vector table specified by VENTn n 1 to 6 is located at address 2n Example Vector tables are s...

Page 207: ...e flag IET0 INT4 interrupt enable flag IE4 Timer counter interrupt enable flag IET1 BT interrupt enable flag IEBT An interrupt enable flag set to 1 enables the corresponding interrupt and an interrupt enable flag set to 0 disables the corresponding interrupt When an interrupt request flag and the interrupt enable flag are set to 1 a vectored interrupt request VRQn occurs This condition is also use...

Page 208: ...ompletion signal for the serial interface IECSI IRQT0 Set by a match signal from timer event counter 0 IET0 IRQT1 Set by a match signal from the timer counter IET1 2 Interrupt priority specification register IPS The interrupt priority specification register selects an interrupt with a higher priority from multiple interrupts using the low order three bits Bit 3 interrupt master enable flag IME spe...

Page 209: ...rder interrupt selection All low order interrupt VRQ1 INTBT INT4 VRQ2 INT0 VRQ3 INT1 VRQ4 INTCSI VRQ5 INTT0 VRQ6 INTT1 Not to be set The listed vectored interrupts are treated as high order interrupts Interrupt master enable flag IME All interrupts are disabled and no vectored interrupt is activated The interrupt enable flag corresponding to an interrupt request flag controls interrupt enabling di...

Page 210: ...M0 A 4 bit memory manipulation instruction is used to set IM0 A RESET signal clears all bits to 0 and a rising edge is specified to be detected Note When the frequency of a sampling clock is F these cycles are equal to 2tCY When the frequency of a sampling clock is fX 64 these cycles are equal to 128 fX Cautions 1 Input a pulse wider than two sampling clock cycles to the INT0 P10 pin Otherwise the...

Page 211: ...cuit INT0 P10 IM00 IM01 Internal bus IM0 4 Edge detection circuit IRQ0 set signal INT0 Input buffer Detection edge specification Sampling clock selection Noise eliminator Selector Selector IM02 IM03 fX 64 Φ INT1 P11 IM10 Internal bus IM1 4 Edge detection circuit IRQ1 set signal INT1 Input buffer Detection edge specification INT4 P00 Internal bus Both edge detection circuit Input buffer IRQ4 set si...

Page 212: ...or Remark tSMP tCY or 64 fX INT0 Shaped output INT0 INT0 INT0 Shaped output Shaped output Shaped output 1 Shorter than sampling cycle tSMP 2 1 to 2 times 3 Longer than 2 times a b tSMP tSMP tSMP tSMP tSMP L L H H L L H L L L H H L L L L Removed as noise Removed as noise ...

Page 213: ...cles after changing the mode register and clear the interrupt request flag FB4H Address 0 0 Specifies rising edge Specifies falling edge Detection edge specification 0 1 1 1 0 1 IM01 IM00 Specifies both rising and falling edges Ignored No interrupt request flag is set 3 IM03 2 IM02 1 IM01 0 IM00 IM0 Symbol 0 1 Selects a noise eliminator Does not select a noise eliminator Noise eliminator selection...

Page 214: ...1 is manipulated the DI instruction must be executed to disable interrupts then the EI instruction must be executed to enable interrupts IST1 and IST0 as well as the other PSW bits are saved in the stack memory when an interrupt is accepted and the status of IST0 and IST1 changes to a status one level higher When a RETI instruction is executed the former values of IST1 and IST0 are resumed Inputti...

Page 215: ...xxx setting IExxx set Hold until IExxx is set Corresponding VRQn occurrence IME 1 Hold until IME is set Is VRQn high order interrupt Note 1 IST1 0 00 or 01 Note 1 IST1 0 00 If two or more VRQns occur select one VRQn according to Table 6 1 Selected VRQn Remaining VRQns Save contents of PC and PSW in stack memory and set dataNote 2 in vector table corresponding to activated VRQn to PC RBE and MBE Ch...

Page 216: ... or 1 Other interrupts interrupts lower than the specified high order interrupt are enabled only when the status is 0 See Figure 6 8 and Table 6 3 When only one interrupt is used as a level two interrupt using this method saves the user the trouble of enabling or disabling interrupts during an interrupt processing and holds down the number of nesting levels to two Figure 6 8 Multiple Interrupt Pro...

Page 217: ...re interrupts are to be enabled at a time or when the processing of three or more interrupts is to be performed When changing IST1 and IST0 interrupts must be disabled beforehand with a DI instruction Figure 6 9 Multiple Interrupt Processing by Changing the Interrupt Status Flags Low or high order interrupt occurrence Normal processing status 0 Single interrupt Dual interrupts Interrupt is enabled...

Page 218: ...interrupt sources caused the interrupt needs to be determined using the interrupt service routine For this determination the DI instruction is to be executed at the start of the interrupt service routine and the interrupt request flags are checked with the SKTCLR instruction If both the request flags are set when this request flag is tested or cleared the interrupt request remains even if one of t...

Page 219: ...ty to INT4 DI SKTCLR IRQ4 IRQ4 1 BR VSUBBT Processing routine EI of INT4 RETI VSUBBT CLR1 IRQBT Processing routine of INTBT EI RETI 2 To use both INTBT and INT4 as having the lower priority and give priority to INT4 SKTCLR IRQ4 IRQ4 1 BR VSUBBT Processing routine of INT4 RETI VSUBBT CLR1 IRQBT Processing routine of INTBT RETI ...

Page 220: ...ed Remarks 1 An interrupt control instruction manipulates hardware address FBxH in data memory which handles interrupt processings There are two types of interrupt control instruction a DI instruction and an EI instruction 2 Three machine cycles required for the interrupt processing include the time to manipulate the stack when an interrupt is accepted Cautions 1 When interrupt control instruction...

Page 221: ...l instructions follow an instruction preceded by the interrupt control instructions is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started When an instruction to be executed after setting IRQn is a DI instruction the interrupt request of the set IRQn is held b When IRQn is set earlier than the last machine cycle of the instruction ...

Page 222: ...nested set RBE to 1 save the register bank by using the PUSH BS instruction and set RBS to 1 to select register bank 1 3 Use of a software interrupt for debugging Setting an interrupt request flag using an instruction has the same effect as the occurrence of an interrupt Debug operation for irregular interrupts or concurrently occurring interrupts can be performed more efficiently by setting the i...

Page 223: ...l interrupts are disabled 3 The interrupt master enable flag is set by the EI instruction At this stage INT0 and INTT0 are enabled 4 An interrupt enable flag is cleared by the DI IExxx instruction to disable INT0 5 The DI instruction disables all interrupts Interrupt disabled INT0 and INTT0 enabled INTT0 enabled Interrupt disabled Main program 1 Reset 2 EI IE0 EI IET0 3 EI 4 DI IE0 5 DI ...

Page 224: ...rupts are disabled 5 Control is returned from the interrupts by the RETI instruction status 0 is set again and interrupts are enabled Remark If all the interrupts are used as having the lower priority as shown in this example saving or restoring the register bank is not necessary if RBE 1 and RBS 2 for the main program and register banks 2 and 3 are used and RBE 0 for the interrupt service program...

Page 225: ...priority are disabled RBE 0 to select register bank 0 3 INTBT with the higher priority occurs The level two interrupts occurs The status is changed to 0 and all the interrupts are disabled 4 RBE 1 and RBS 1 to select register bank 1 only the registers used may be saved by the PUSH instruction 5 RBS is returned to 2 and execution returns to the main program The status is returned to 1 Reset Status ...

Page 226: ...disabled the interrupt request flag is held 2 When the interrupt is enabled by the EI instruction the INT0 interrupt service program starts 3 Same as 1 4 When the held INTCSI flag is enabled the INTCSI interrupt service program starts RETI Reset 2 EI 1 INT0 INT0 service program 3 INTCSI EI IE0 RETI INTCSI service program EI IECSI 4 Main program ...

Page 227: ... concurrently during execution of the same instruction INT0 with a higher priority is executed first INTT0 is held 2 When the INT0 interrupt service program has been executed the RETI instruction is executed to start the interrupt service program for INTT0 which has been held Reset 2 RETI INT0 service program 1 EI IET0 Main program INT0 INTT0 EI IE0 EI RETI INTT0 service routine ...

Page 228: ...upt with the higher priority is processed DI IExx is not necessary 2 When an interrupt with the lower priority occurs while the interrupt with the higher priority is executed the interrupt with the lower priority is kept pending 3 When the interrupt with the higher priority has been processed INTCSI with the higher priority of the pending interrupts is executed 4 When the processing of INTCSI has ...

Page 229: ...not allowed to be level two interrupts are disabled 3 When INTT0 allowed to be a level two interrupt occurs the level two interrupt is executed and status 1 is set to disable all interrupts 4 When INTT0 processing is completed status 0 is set again 5 INTCSI and INT4 which have been disabled are enabled then control returns Reset INTCSI service program EI IET0 Main program EI IE0 EI IECSI Status 0 ...

Page 230: ...the software once the test processing has been executed Test enable flags IExxx correspond to test request flags The test enable flags enable the standby release signal when they are set to 1 They disables the standby release signal when they are set to 0 When both a test request flag and the corresponding test enable flag are set to 1 the standby release signal is generated Table 6 6 shows the si...

Page 231: ...RQ2 is set when a rising edge is detected on the INT2 input pin b Detection of a falling edge on any of the KR0 to KR7 input pins key interrupt One of the pins KR0 to KR7 is selected to be used for interrupt input with the INT2 edge detection mode register IM2 When a falling edge of one of input signals applied to the selected pin is detected IRQ2 is set Figure 6 11 shows the format of IM2 IM2 is ...

Page 232: ...iagram of the INT2 and KR0 to KR7 Circuits INT2 P12 KR7 P73 KR6 P72 KR5 P71 KR4 P70 KR3 P63 KR2 P62 KR1 P61 KR0 P60 IM2 4 Input buffer Internal bus Selector Rising edge detection circuit Falling edge detection circuit INT2 IRQ2 set signal IM20 IM21 ...

Page 233: ... Then clear the test request flags using a CLR1 instruction before enabling test inputs 2 When a low level signal is applied to any of the pins subjected to falling edge detection IRQ2 is not set when a falling edge is detected on another pin 0 0 IM21 IM20 FB6H IM2 IM21 0 0 1 1 IM20 0 1 0 1 Specifies rising edge of INT2 pin input Interrupt input pin INT2 1 KR4 KR7 4 KR2 KR7 6 KR0 KR7 8 Specifies f...

Page 234: ...214 µPD750008 USER S MANUAL MEMO ...

Page 235: ...ions such as watch operation In either mode all contents of the registers flags and data memory that are present immediately before the standby mode is set are preserved In addition the states of the output latches of the I O ports and the states of the output buffers are also preserved so that the states of the I O ports are to be processed to minimize the power consumption of the entire system C...

Page 236: ...is internally connected to VSS ground potential to suppress leakage at the crystal oscillator circuitry This means that the STOP mode cannot be used with a system that uses an external clock Instruction for setting System clock for setting Clock oscillator Basic interval timer watchdog timer Serial interface Timer event counter Timer counter Clock timer External interrupt CPU Release signal HALT m...

Page 237: ...errupt enable flag Figure 7 1 shows how the STOP and HALT modes are released Figure 7 1 Standby Mode Release Operation 1 2 a Release of the STOP mode by RESET signal b Release of the STOP mode by the occurrence of an interrupt Note The following two wait times can be selected by a mask option 217 fX 21 8 ms at 6 00 MHz 31 3 ms at 4 19 MHz 215 fX 5 46 ms at 6 00 MHz 7 81 ms at 4 19 MHz However the ...

Page 238: ...here the interrupt request that releases the standby mode is accepted When the STOP mode is released by the occurrence of an interrupt a wait time is determined by the basic interval timer mode register BTM See Table 7 2 A time required for stable oscillation varies with the type of resonator used and the supply voltage at the time of STOP mode release Accordingly a wait time is to be selected acc...

Page 239: ...ermines whether to perform a vectored interrupt when the CPU resumes instruction execution a When IME 0 If a standby mode is released execution restarts with the instruction immediately following the instruction used to set the standby mode The interrupt request flag is held b When IME 1 If a standby mode is released a vectored interrupt is executed after the two instructions are executed However ...

Page 240: ... processing is performed or not 5 Specify a CPU clock to be used after release If the CPU clock is changed required machine cycles must elapse before the standby mode is set 6 Select a wait time to be used when a standby mode is released 7 Set a standby mode using a STOP or HALT instruction A standby mode when combined with the system clock switch function enables a lower power consumption and low...

Page 241: ...4 SKT PORT0 0 P00 1 BR PDOWN Power down SET1 BTM 3 Power on WAIT SKT IRQBT Wait for 31 3 ms BR WAIT SKT PORT0 0 Chattering check BR PDOWN MOV A 0011B MOV PCC A Set high speed mode MOV XA xxH Set port mode register MOV PMGm XA EI IE0 EI IET0 RETI PDOWN MOV A 0 Lowest speed mode MOV PCC A MOV XA 00H MOV PMGA XA I O port high impedance MOV PMGB XA DI IE0 Disable INT0 and INTT0 DI IET0 MOV A 1011B MOV...

Page 242: ...the main system clock is stopped and HALT mode is set In the standby mode intermittent operation is performed at intervals of 0 5 s The subsystem clock is switched back to the main system clock on the rising edge of INT4 INTBT is not used Timing chart INT4 INT4 250 ms Operating mode low speed Intermittent operation HALT mode low speed operation Operating mode VDD 0 V P00 INT4 CPU operation Voltage...

Page 243: ...INT4 SKT PORT0 0 Power normal MBE 0 BR PDOWN CLR1 SCC 3 Start main system clock oscillation MOV A 8 MOV BTM A WAIT1 SKT IRQBT Wait for 250 ms BR WAIT1 SKT PORT0 0 Chattering check BR PDOWN CLR1 SCC 0 Switch to main system clock RETI PDOWN SET1 SCC 0 Switch to subsystem clock MOV A 6 WAIT2 INCS A Wait for 32 machine cycles BR WAIT2 SET1 SCC 3 Stop main system clock oscillation RETI Caution Before t...

Page 244: ...224 µPD750008 USER S MANUAL MEMO ...

Page 245: ... is initialized as indicated in Table 8 1 Figure 8 2 shows the reset operation timing Figure 8 2 Reset Operation by Generation of RESET Signal Note The following two wait times can be selected by a mask option 217 fX 21 8 ms at 6 00 MHz 31 3 ms at 4 19 MHz 215 fX 5 46 ms at 6 00 MHz 7 81 ms at 4 19 MHz However the µPD75P0016 dose not have a mask option and its wait time is fixed to 215 fX WDTM RES...

Page 246: ...in RBE and bit 7 is set in MBE Undefined 1000B HeldNote Held 0 0 Undefined 0 0 0 FFH 0 0 0 0 FFH 0 0 0 0 Held 0 0 Held Carry flag CY Skip flags SK0 to SK2 Interrupt status flags IST0 IST1 Bank enable flags MBE RBE Counter BT Mode register BTM Watchdog timer enable flag WDTM Counter T0 Modulo register TMOD0 Mode register TM0 TOE0 TOUT flip flop Counter T1 Modulo registers TMOD1 Mode register TM1 TO...

Page 247: ...T1 and INT2 mode registers IM0 IM1 IM2 Output buffer Output latch I O mode registers PMGA PMGB PMGC Pull up resistor specification register POGA POGB Hardware Generation of a RESET signal during operation 0 0 0 0 Reset 0 0 0 0 0 0 Off Clear 0 0 0 Undefined Sub oscillator control register SOS Clock generator clock output circuit Interrupt Digital ports Generation of a RESET signal in a standby mode...

Page 248: ...228 µPD750008 USER S MANUAL MEMO ...

Page 249: ...emory or verifying its contents The X2 pin is used to input the inverted signal of the X1 pin input MD0 MD3 Operation mode selection pins used when writing to the program memory or verifying its contents P40 to P43 I O pins for 8 bit data used when writing to the program memory or verifying low order four bits its contents P50 to P53 high order four bits VDD Power voltage is applied to this pin Du...

Page 250: ...ram memory is described below high speed write is possible 1 Pull low all unused pins to VSS by means of resistors Bring X1 to low level 2 Apply 5 V to VDD and to VPP 3 Wait 10 µs 4 Select program memory address clear mode 5 Apply 6 V to VDD and 12 5 V to VPP 6 Select program inhibit mode 7 Select write mode for 1 ms duration and write data 8 Select program inhibit mode 9 Select verify mode If wri...

Page 251: ...G PROGRAM MEMORY PROM The timing for steps 2 to 12 is shown below VPP VDD VPP VDD 1 VDD VDD X1 P40 P43 P50 P53 MD0 P30 MD1 P31 MD2 P32 MD3 P33 Data input Data output Data input Write Verify Additional write Address increment Repeat x times ...

Page 252: ...program memory address clear mode 5 Apply 6 V to VDD and 12 5 V to VPP 6 Select program inhibit mode 7 Select verify mode Data is output sequentially one address at a time for each cycle of four clock pulses appearing on the X1 pin 8 Select program inhibit mode 9 Select program memory address clear mode 10 Apply 5 V to VDD and to VPP 11 Turn the power off The timing for steps 2 to 9 is shown below...

Page 253: ...fficult for NEC to completely test the one time PROM product before shipment It is therefore recommended that screening be performed to verify the PROM contents after the necessary data has been written to the PROM and the product has been stored under the following conditions Storage Temperature Storage Time 125 C 24 hours ...

Page 254: ...234 µPD75008 USER S MANUAL MEMO ...

Page 255: ...p resistor is not connected the port goes into a high impedance state on reset The ports of the µPD75P0016 do not have a mask option and is always open 10 2 MASK OPTION OF STANDBY FUNCTION The standby function of the µPD750008 allows you to select wait time by using a mask option The wait time is required for the CPU to return to the normal operation mode after the standby function has been releas...

Page 256: ...mask option 1 Enable the feedback resistor switches on or off by software 2 Disable the feedback resistor cuts by hardware To use the feedback resistor after selecting 1 turn the feedback resistor on by setting SOS 0 to 0 for details see 6 in Section 5 2 2 Select 1 to use the subsystem clock For the µPD75P0016 the mask option need not be set use of the feedback resistor is factory set ...

Page 257: ...sing modes applicable to data memory manipulation and register banks used for instruction execution 11 1 UNIQUE INSTRUCTIONS This section outlines the unique instructions among the µPD750008 instruction set 11 1 1 GETI Instruction The GETI instruction converts any of the following instructions to a 1 byte instruction a Subroutine call instruction for the entire space b Branch instruction for the e...

Page 258: ... in a very efficient manner 11 1 3 String Effect Instructions With the µPD750008 two types of string effect instructions are available a MOV A n4 or MOV XA n8 b MOV HL n8 String effect means the locating of these two types of instructions at contiguous addresses Example A0 MOV A 0 A1 MOV A 1 XA7 MOV XA 07 When string effect instructions are arranged as in this example if execution starts at addres...

Page 259: ...ipped If no carry is generated ADDS A n4 is executed In this case the skip function of this instruction ADDS A n4 is disabled so that even if this addition generates a carry the instruction following this instruction is not skipped Accordingly programs can be written after ADDS A n4 Example An accumulator is added to memory data in decimal ADDS A 6 ADDC A HL A CY A HL CY ADDS A 10 b Number system ...

Page 260: ...ng instruction is skipped to execute the instruction immediately after the skipped instruction A skip requires the following number of machine cycles a When the instruction to be skipped immediately following the skip instruction is a 3 byte instruction that is the BR addr BRA addr1 CALL addr or CALLA addr1 instruction 2 machine cycles b When the instruction to be skipped immediately following the...

Page 261: ...see Table 3 1 and Figure 3 7 Representation format Description method reg X A B C D E H L reg1 X B C D E H L rp XA BC DE HL rp1 BC DE HL rp2 BC DE rp XA BC DE HL XA BC DE HL rp 1 BC DE HL XA BC DE HL rpa HL HL HL DE DL rpa1 DE DL n4 4 bit immediate data or label n8 8 bit immediate data or label mem 8 bit immediate data or labelNote bit 2 bit immediate data or label fmem FB0H FBFH and FF0H FFFH imm...

Page 262: ... BC DE Extended register pair DE HL Extended register pair HL PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status word MBE Memory bank enable flag RBE Register bank enable flag PORTn Port n n 0 to 8 IME Interrupt master enable flag IPS Interrupt priority specification register IExxx Interrupt enable flag RBS Register bank select register MBS Memory bank select regi...

Page 263: ...H 0FFFH 7 addr addr1 Current PC 15 to Current PC 1 Current PC 2 to Current PC 16 8 caddr 0000H 0FFFH caddr 0000H 0FFFH PC12 0 or 1000H 17FFH PC12 1 caddr 0000H 0FFFH PC12 0 or 1000H 1FFFH PC12 1 caddr 0000H 0FFFH PC13 PC12 00B or 1000H 1FFFH PC13 PC12 01B or 2000H 2FFFH PC13 PC12 10B or 3000H 3FFFH PC13 PC12 11B 9 faddr 0000H 07FFH 10 taddr 0020H 007FH 11 For MkII mode only addr1 0000H 0FFFH µPD75...

Page 264: ...operation is performed S 0 When a 1 byte instruction or 2 byte instruction is skipped S 1 When a 3 byte instructionNote is skipped S 2 Note 3 byte instruction BR addr BRA addr1 CALL addr and CALLA addr1 instructions Caution The GETI instruction is skipped in one machine cycle One machine cycle is equal to one cycle tCY of the CPU clock F and four different machine cycles are available for selectio...

Page 265: ...A HL 1 2 S A HL then L L 1 1 L 0 A HL 1 2 S A HL then L L 1 1 L FH A rpa1 1 1 A rpa1 2 XA HL 2 2 XA HL 1 HL A 1 1 HL A 1 HL XA 2 2 HL XA 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 mem A 2 2 mem A 3 mem XA 2 2 mem XA 3 A reg 2 2 A reg XA rp 2 2 XA rp reg1 A 2 2 reg1 A rp 1 XA 2 2 rp 1 XA XCH A HL 1 1 A HL 1 A HL 1 2 S A HL then L L 1 1 L 0 A HL 1 2 S A HL then L L 1 1 L FH A rpa1 1 1 A rpa1 2 XA HL 2 ...

Page 266: ...m bit CY 2 2 fmem bit CY 4 pmem L CY 2 2 pmem7 2 L3 2 bit L1 0 CY 5 H mem bit CY 2 2 H mem3 0 bit CY 1 ADDS A n4 1 1 S A A n4 carry XA n8 2 2 S XA XA n8 carry A HL 1 1 S A A HL 1 carry XA rp 2 2 S XA XA rp carry rp 1 XA 2 2 S rp 1 rp 1 XA carry ADDC A HL 1 1 A CY A HL CY 1 XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY SUBS A HL 1 1 S A A HL 1 borrow XA rp 2 2 S XA XA rp borrow rp 1 XA 2 ...

Page 267: ... 1 1 CY A0 A3 CY An 1 An NOT A 2 2 A A INCS reg 1 1 S reg reg 1 reg 0 rp1 1 1 S rp1 rp1 1 rp1 00H HL 2 2 S HL HL 1 1 HL 0 mem 2 2 S mem mem 1 3 mem 0 DECS reg 1 1 S reg reg 1 reg FH rp 2 2 S rp rp 1 rp FFH SKE reg n4 2 2 S Skip if reg n4 reg n4 HL n4 2 2 S Skip if HL n4 1 HL n4 A HL 1 1 S Skip if A HL 1 A HL XA HL 2 2 S Skip if XA HL 1 XA HL A reg 2 2 S Skip if A reg A reg XA rp 2 2 S Skip if XA r...

Page 268: ... SKF mem bit 2 2 S Skip if mem bit 0 3 mem bit 0 fmem bit 2 2 S Skip if fmem bit 0 4 fmem bit 0 pmem L 2 2 S Skip if pmem7 2 L3 2 bit L1 0 0 5 pmem L 0 H mem bit 2 2 S Skip if H mem3 0 bit 0 1 H mem bit 0 SKTCLR fmem bit 2 2 S Skip if fmem bit 1 and clear 4 fmem bit 1 pmem L 2 2 S Skip if pmem7 2 L3 2 bit L1 0 5 pmem L 1 1 and clear H mem bit 2 2 S Skip if H mem3 0 bit 1 1 H mem bit 1 and clear AN...

Page 269: ...PD75P0016 PC13 0 addr The assembler selects the most adequate instruction from instructions below BR addr BRCB caddr BR addr addr1Note µPD750004 11 PC11 0 addr1 The assembler selects the most adequate instruction from instructions below BRA addr1 BR addr BRCB caddr BR addr1 µPD750006 µPD750008 PC12 0 addr1 The assembler selects the most adequate instruction from instructions below BRA addr1 BR add...

Page 270: ... 0 addr µPD75P0016 PC13 0 addr addr 1 2 µPD750004 7 PC11 0 addr µPD750006 µPD750008 PC12 0 addr µPD75P0016 PC13 0 addr addr1 1 2 µPD750004 7 PC11 0 addr1 µPD750006 µPD750008 PC12 0 addr1 µPD75P0016 PC13 0 addr1 PCDE 2 3 µPD750004 PC11 0 PC11 8 DE µPD750006 µPD750008 PC12 0 PC12 8 DE µPD75P0016 PC13 0 PC13 8 DE PCXA 2 3 µPD750004 PC11 0 PC11 8 XA µPD750006 µPD750008 PC12 0 PC12 8 XA µPD75P0016 PC13...

Page 271: ...1 0 caddr11 0 µPD750006 µPD750008 PC12 0 PC12 caddr11 0 µPD75P0016 PC13 0 PC13 12 caddr11 0 CALLANote 2 addr1 3 3 µPD750004 11 SP 2 x x MBE RBE SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 0 0 PC11 0 addr SP SP 6 µPD750006 µPD750008 SP 2 x x MBE RBE SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 0 PC12 PC12 0 addr SP SP 6 µPD75P0016 SP 2 x x MBE RBE SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 PC13 PC12 PC13 0 addr1 SP SP 6 Note 1 The shade...

Page 272: ...SP 4 PC11 0 SP 5 0 0 0 0 PC11 0 addr SP SP 6 µPD750006 µPD750008 SP 2 x x MBE RBE SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 0 PC12 PC12 0 addr SP SP 6 µPD75P0016 SP 2 x x MBE RBE SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 PC13 PC12 PC13 0 addr SP SP 6 CALLFNote faddr 2 2 µPD750004 9 SP 3 MBE RBE 0 0 SP 4 SP 1 SP 2 PC11 0 PC11 0 0 faddr SP SP 4 µPD750006 µPD750008 SP 3 MBE RBE 0 PC12 SP 4 SP 1 SP 2 PC11 0 PC12 0 00 faddr...

Page 273: ... 0 0 PC13 PC12 PC13 0 000 faddr SP SP 6 RETNote 1 3 µPD750004 PC11 0 SP SP 3 SP 2 MBE RBE 0 0 SP 1 SP SP 4 µPD750006 µPD750008 PC11 0 SP SP 3 SP 2 MBE RBE 0 PC12 SP 1 SP SP 4 µPD75P0016 PC11 0 SP SP 3 SP 2 MBE RBE PC13 PC12 SP 1 SP SP 4 3 µPD750004 x x MBE RBE SP 4 0 0 0 0 SP 1 PC11 0 SP SP 3 SP 2 SP SP 6 µPD750006 µPD750008 x x MBE RBE SP 4 MBE 0 0 PC12 SP 1 PC11 0 SP SP 3 SP 2 SP SP 6 µPD75P0016...

Page 274: ...0004 0 0 0 0 SP 1 PC11 0 SP SP 3 SP 2 x x MBE RBE SP 4 SP SP 6 Then skip unconditionally µPD750006 µPD750008 0 0 0 PC12 SP 1 PC11 0 SP SP 3 SP 2 x x MBE RBE SP 4 SP SP 6 Then skip unconditionally µPD75P0016 0 0 PC13 PC12 SP 1 PC11 0 SP SP 3 SP 2 x x MBE RBE SP 4 SP SP 6 Then skip unconditionally RETINote 1 3 µPD750004 Unconditionally MBE RBE 0 0 SP 1 PC11 0 SP SP 3 SP 2 PSW SP 4 SP 5 SP SP 6 µPD75...

Page 275: ... RBS SP SP 2 POP rp 1 1 rp SP 1 SP SP SP 2 BS 2 2 MBS SP 1 RBS SP SP SP 2 EI 2 2 IME IPS 3 1 IExxx 2 2 IExxx 1 DI 2 2 IME IPS 3 0 IExxx 2 2 IExxx 0 INNote 2 A PORTn 2 2 A PORTn n 0 8 XA PORTn 2 2 XA PORTn 1 PORTn n 4 6 OUTNote 2 PORTn A 2 2 PORTn A n 2 8 PORTn XA 2 2 PORTn 1 PORTn XA n 4 6 HALT 2 2 Set HALT Mode PCC 2 1 STOP 2 2 Set STOP Mode PCC 3 1 NOP 1 1 No Operation Note 1 The shaded portion ...

Page 276: ...TBR instruction is used PC12 0 taddr 4 0 taddr 1 When the TCALL instruction is used SP 4 SP 1 SP 2 PC11 0 SP 3 MBE RBE 0 PC12 PC12 0 taddr 4 0 taddr 1 SP SP 4 When an instruction other than Depends on the the TBR or TCALL instruction is referenced used instruction Execution of taddr taddr 1 instruction µPD75P0016 When the TBR instruction is used PC13 0 taddr 5 0 taddr 1 When the TCALL instruction ...

Page 277: ...ion is used SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 0 PC12 SP 2 x x MBE RBE PC12 0 taddr 4 0 taddr 1 SP SP 6 3 When an instruction other than Depends on the the TBR or TCALL instruction is referenced used instruction Execution of taddr taddr 1 instruction 3 µPD75P0016 When the TBR instruction is used PC13 0 taddr 5 0 taddr 1 4 When the TCALL instruction is used SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 PC13 PC12 SP 2...

Page 278: ...inus one Sn Immediate data for the one s complement of the address 15 to 1 relative to the branch destination address reg R2 R1 R0 reg 0 0 0 A 0 0 1 X 0 1 0 L 0 1 1 H 1 0 0 E 1 0 1 D 1 1 0 C 1 1 1 B reg1 rp P2 P1 P0 reg pair 0 0 0 XA 0 0 1 XA 0 1 0 HL 0 1 1 HL 1 0 0 DE 1 0 1 DE 1 1 0 BC 1 1 1 BC rp 1 Q2 Q1 Q0 addressing 0 0 1 HL 0 1 0 HL 0 1 1 HL 1 0 0 DE 1 0 1 DL rpa rp2 P2 P1 reg pair 0 0 XA 0 1...

Page 279: ...dressing 1 Second byte of instruction code Accessible bits fmem bit 1 0 B1 B0 F3 F2 F1 F0 FB0H FBFH manipulatable bits 1 1 B1 B0 F3 F2 F1 F0 FF0H FFFH manipulatable bits pmem L 0 1 0 0 G3 G2 G1 G0 FC0H FFFH manipulatable bits H mem bit 0 0 B1 B0 D3 D2 D1 D0 Manipulatable bits of accessible memory bank Bn Immediate data for bit Fn Immediate data for fmem Low order four bits of address Gn Immediate ...

Page 280: ...0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 mem XA 1 0 0 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 0 A reg 1 0 0 1 1 0 0 1 0 1 1 1 1 R2 R1 R0 XA rp 1 0 1 0 1 0 1 0 0 1 0 1 1 P2 P1 P0 reg1 A 1 0 0 1 1 0 0 1 0 1 1 1 0 R2 R1 R0 rp 1 XA 1 0 1 0 1 0 1 0 0 1 0 1 0 P2 P1 P0 XCH A rpa1 1 1 1 0 1 Q2 Q1 Q0 XA HL 1 0 1 0 1 0 1 0 0 0 0 1 0 0 0 1 A mem 1 0 1 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 XA mem 1 0 1 1 0 0 1 0 D7 D6 D5 D4 D3 D2 D1...

Page 281: ... 1 0 1 0 1 0 1 1 1 0 0 P2 P1 P0 SUBC A HL 1 0 1 1 1 0 0 0 XA rp 1 0 1 0 1 0 1 0 1 1 1 1 1 P2 P1 P0 rp 1 XA 1 0 1 0 1 0 1 0 1 1 1 1 0 P2 P1 P0 AND A n4 1 0 0 1 1 0 0 1 0 0 1 1 I3 I2 I1 I0 A HL 1 0 0 1 0 0 0 0 XA rp 1 0 1 0 1 0 1 0 1 0 0 1 1 P2 P1 P0 rp 1 XA 1 0 1 0 1 0 1 0 1 0 0 1 0 P2 P1 P0 OR A n4 1 0 0 1 1 0 0 1 0 1 0 0 I3 I2 I1 I0 A HL 1 0 1 0 0 0 0 0 XA rp 1 0 1 0 1 0 1 0 1 0 1 0 1 P2 P1 P0 rp...

Page 282: ...0 0 1 1 0 0 1 A reg 1 0 0 1 1 0 0 1 0 0 0 0 1 R2 R1 R0 XA rp 1 0 1 0 1 0 1 0 0 1 0 0 1 P2 P1 P0 Carry flag SET1 CY 1 1 1 0 0 1 1 1 manipu CLR1 CY 1 1 1 0 0 1 1 0 lation SKT CY 1 1 0 1 0 1 1 1 NOT1 CY 1 1 0 1 0 1 1 0 Memory SET1 mem bit 1 0 B1 B0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 bit 1 1 0 0 1 1 1 0 1 2 manipu CLR1 mem bit 1 0 B1 B0 0 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0 lation 1 1 0 0 1 1 1 0 0 2 SKT mem b...

Page 283: ...0 0 0 0 RETI 1 1 1 0 1 1 1 1 PUSH rp 0 1 0 0 1 P2 P1 1 BS 1 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 POP rp 0 1 0 0 1 P2 P1 0 BS 1 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 I O IN A PORTn 1 0 1 0 0 0 1 1 1 1 1 1 N3 N2 N1 N0 XA PORTn 1 0 1 0 0 0 1 0 1 1 1 1 N3 N2 N1 N0 OUT PORTn A 1 0 0 1 0 0 1 1 1 1 1 1 N3 N2 N1 N0 PORTn XA 1 0 0 1 0 0 1 0 1 1 1 1 N3 N2 N1 N0 Interrupt EI 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 0 control IExxx 1 ...

Page 284: ...s different from Mk II mode in the functions Read the explanation of Mk I mode for Mk I mode and the explanation of Mk II mode for Mk II mode as required Remark Function in this section is applicable to the µPD750006 and µPD750008 whose program counters consist of 13 bits each This is also applicable to the µPD750004 whose program counter consists of 12 bits and the µPD75P0016 whose program counte...

Page 285: ...n be utilized When two or more of this instruction are executed in succession the string instructions following an executed instruction are processed as NOP instructions MOV rp2 n8 Function rp2 n8 n8 I7 0 00H FFH Transfers the 8 bit immediate data n8 to register pair rp2 BC DE MOV A HL MOV A HL MOV A HL MOV A rpa1 Function A Register pair specified by the operand When HL is specified for the regis...

Page 286: ...gister are odd numbered an address with the low order bit ignored is specified Example The data at addresses 3EH and 3FH are transferred to the XA register pair MOV HL 3EH MOV XA HL MOV HL A Function HL A Transfers the contents of the A register to the data memory location addressed by the HL register pair MOV HL XA Function HL A HL 1 X Transfers the contents of the A register to the data memory l...

Page 287: ...egister to the data memory location addressed by the 8 bit immediate data mem MOV mem XA Function mem A mem 1 X mem D7 0 00H FEH Transfers the contents of the A register to the data memory location addressed by the 8 bit immediate data mem and transfers the contents of the X register to the next memory address An even address can be specified with mem MOV A reg Function A reg Transfers the content...

Page 288: ...ed by the specified register pair HL HL HL DE DL When HL automatic increment is specified for the register pair automatically increments the contents of the L register by one after the data exchange and continues the operation until the contents are set to 0 Then skips the immediately following instruction When HL automatic decrement is specified for the register pair automatically decrements the ...

Page 289: ...s of the A register with the data at the data memory location addressed by the 8 bit immediate data mem XCH XA mem Function A mem X mem 1 mem D7 0 00H FEH Exchanges the contents of the A register with the data at the data memory location addressed by the 8 bit immediate data mem and exchanges the contents of the X register 1 with the data at the next memory address An even address can be specified...

Page 290: ... affected by the execution of the pseudo instruction This instruction is useful for consecutive table data references Example For the µPD750006 and µPD750008 Remark Function in this section is applicable to the µPD750006 and µPD750008 whose program counters consist of 13 bits each This is also applicable to the µPD750004 whose program counter consists of 12 bits and the µPD75P0016 whose program co...

Page 291: ... register and the high order four bits to the X register The table data is addressed by the program counter PC with its low order eight bits PC7 0 exchanged with the contents of the XA register pair The table address is determined by the contents of the program counter present when this instruction is executed The table area must have necessary data loaded by an assembler pseudo instruction DB ins...

Page 292: ...er four bits of the table data eight bits in program memory to the A register and the high order four bits to the X register The table data is addressed by the low order three bits of the B register and the contents of the C D and E registers The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this...

Page 293: ...n addressing fmem bit pmem L H mem bit Example The flag bit 3 at address 3FH in data memory is set in bit 2 of port 3 FLAG EQU 3FH 3 SEL MB0 MOV H FLAG SHR6 H high order 4 bits of FLAG MOV1 CY H FLAG CY FLAG MOV1 PORT3 2 CY P32 CY 11 4 4 Arithmetic Logical Instructions ADDS A n4 Function A A n4 Skip if carry n4 I3 0 0 FH Adds the 4 bit immediate data n4 to the contents of the A register in binary ...

Page 294: ...ction rp rp 1 XA Skip if carry Adds the contents of the XA register pair to the contents of register pair rp 1 HL DE BC XA HL DE BC in binary then skips the next instruction if the addition generates a carry The carry flag is not affected Example The register pair is left shifted MOV XA rp 1 ADDS rp 1 XA NOP ADDC A HL Function A CY A HL CY Adds the data at the data memory location addressed by the...

Page 295: ...ry is generated the carry flag is reset SUBS A HL Function A A HL Skip if borrow Subtracts the data at the data memory location addressed by the HL register pair from the contents of the A register then sets the result in the A register If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected SUBS XA rp Function XA XA rp Skip if borrow S...

Page 296: ...instruction is executed and the skip function of the ADDS A n4 instruction is disabled Accordingly a combination of these instructions can be used for number system conversion See Section 11 1 SUBC XA rp Function XA CY XA rp CY Subtracts the contents of register pair rp XA HL DE BC XA HL DE BC together with the carry flag from the contents of the XA register pair then sets the result in the XA reg...

Page 297: ... HL DE BC with the contents of the XA register pair then sets the result in the specified register pair OR A n4 Function A A 4 n4 I3 0 0 FH ORs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example The low order three bits of an accumulator are set to 1 OR A 0111B OR A HL Function A A HL ORs the contents of the A register with the data at th...

Page 298: ...n accumulator is inverted XOR A 1000B XOR A HL Function A A HL Exclusive ORs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register XOR XA rp Function XA XA rp Exclusive ORs the contents of the XA register pair with the contents of register pair rp XA HL DE BC XA HL DE BC then sets the result in the XA regis...

Page 299: ...g 0 Increments the contents of register reg X A H L D E B C If the result of increment produces reg 0 the immediately following instruction is skipped INCS rp1 Function rp1 rp1 1 Skip if rp1 00H Increments the contents of register pair rp1 HL DE BC If the result of increment produces rp1 00H the immediately following instruction is skipped INCS HL Function HL HL 1 Skip if HL 0 Increments the data ...

Page 300: ...tents of register pair rp XA HL DE BC XA HL DE BC If the result of decrement produces rp FFH the immediately following instruction is skipped 11 4 7 Compare Instructions SKE reg n4 Function Skip if reg n4 n4 I3 0 0 FH Skips the immediately following instruction if the contents of register reg X A H L D E B C match the 4 bit immediate data n4 SKE HL n4 Function Skip if HL n4 n4 I3 0 0 FH Skips the ...

Page 301: ...der bit ignored is specified SKE A reg Function Skip if A reg Skips the immediately following instruction if the contents of the A register match the contents of register reg X A H L D E B C SKE XA rp Function Skip if XA rp Skips the immediately following instruction if the contents of the XA register pair match the contents of register pair rp XA HL DE BC XA HL DE BC 11 4 8 Carry Flag Manipulatio...

Page 302: ...T1 H mem bit Function Bit specified in operand 1 Sets the bit in data memory specified by bit manipulation addressing fmem bit pmem L H mem bit CLR1 mem bit Function mem bit 0 mem D7 0 00H FFH bit B1 0 0 3 Clears the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem CLR1 fmem bit CLR1 pmem L CLR1 H mem bit Function Bit specified in operand 0 Cle...

Page 303: ...0H FFH bit B1 0 0 3 Skips the immediately following instruction if the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem is 0 SKF fmem bit SKF pmem L SKF H mem bit Function Skip if bit specified in operand 0 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit pmem L H mem bit is...

Page 304: ...em L H mem bit then sets the result in the carry flag XOR1 CY fmem bit XOR1 CY pmem L XOR1 CY H mem bit Function CY CY bit specified in operand Exclusive ORs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pmem L H mem bit then sets the result in the carry flag 11 4 10 Branch Instructions BR addr Function For the µPD750008 PC12 0 addr add...

Page 305: ...ogram counter consists of 13 bits addr 0000H to 17FFH and the µPD75P0016 whose program counter consists of 14 bits addr 0000H to 3FFFH BRA addr1 Function For the µPD750008 PC12 0 addr1 BR addr Function For the µPD750008 PC12 0 addr addr 0000H 1FFFH Transfers the immediate data addr to the program counter PC then branches to the location addressed by the program counter BR addr Function For the µPD...

Page 306: ...gram memory space In the µPD750006 and µPD750008 PC12 cannot be changed so no branch occurs beyond the block Similarly in the µPD75P0016 PC12 and PC13 cannot be changed so no branch occurs beyond the block Caution The BRCB caddr instruction usually causes a branch within the block containing the instruction However if the first byte is located at address 0FFEH or 0FFFH a branch to block 1 instead ...

Page 307: ...tents of the DE register pair BR PCXA Function For the µPD750008 PC12 0 PC12 8 XA PC7 4 X PC3 0 A Branches to the address specified by the program counter whose low order 8 bits PC7 0 have been replaced with the contents of the XA register pair The high order bits of the program counter are not affected Caution As with the BR PCDE instruction if the first byte is located at address xxFEH or xxFFH ...

Page 308: ...instruction for table definition This instruction is used to replace a 3 byte BR instruction with a 1 byte GETI instruction The 12 bit address data must be coded in addr For detailed information refer to RA75X Assembler Package User s Manual Language EEU 1363 Remark Function in this section is applicable to the µPD750008 whose program counter consists of 13 bits addr 0000H to 1FFFH However this is...

Page 309: ...ntents of the program counter return address memory bank enable flag MBE and register bank enable flag RBE to the data memory location stack addressed by the stack pointer SP then branches to the location addressed by the 14 bit immediate data addr after decrementing SP Remark Function in this section is applicable to the µPD750008 whose program counter consists of 13 bits addr 0000H to 1FFFH Howe...

Page 310: ...Only the address range 0000H 07FFH 0 2047 can be called TCALL addr Function Assembler pseudo instruction of the GETI instruction for table definition This instruction is used to replace a 3 byte CALL addr instruction with a 1 byte GETI instruction The 12 bit address data must be coded in addr For detailed information refer to RA75X Assembler Package User s Manual Language EEU 1363 Remark Function ...

Page 311: ...However this is also applicable to the µPD750004 whose program counter consists of 12 bits addr 0000H to 0FFFH the µPD750006 whose program counter consists of 13 bits addr 0000H to 17FFH and the µPD75P0016 whose program counter consists of 14 bits addr 0000H to 3FFFH RETS Function For the µPD750008 Mk I mode PC11 8 SP MBE 0 0 PC12 SP 1 PC3 0 SP 2 PC7 4 SP 3 SP SP 4 Then skip unconditionally Mk II ...

Page 312: ...ion stack addressed by the stack pointer SP then increments the contents of SP This instruction is used when control is returned from an interrupt service routine Remark Function in this section is applicable to the µPD750008 whose program counter consists of 13 bits addr 0000H to 1FFFH However this is also applicable to the µPD750004 whose program counter consists of 12 bits addr 0000H to 0FFFH t...

Page 313: ...BS SP MBS SP 1 SP SP 2 Restores the register bank select register RBS and the memory bank select register MBS with the data at the data memory location stack addressed by the stack pointer SP then increments SP 11 4 12 Interrupt Control Instructions EI Function IME IPS 3 1 Sets the interrupt master enable flag bit 3 of the interrupt priority specification register to 1 to enable interrupts Whether...

Page 314: ...d by PORTn n 4 or 6 to the A register then transfers the contents of the next port to the X register Caution Only the number 4 or 6 can be specified as n Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set Depending on I O mode specification output latch data in the output mode or pin data in the input mode are transferred OUT PORTn A Function PORTn A n N3 0 2 8 Transfers the...

Page 315: ...P instruction STOP Function PCC 3 1 Sets the STOP mode This instruction is used to set bit 3 of the processor clock control register Caution The instruction immediately following a STOP instruction must be a NOP instruction NOP Function Uses one machine cycle without performing an action 11 4 15 Special Instructions SEL RBn Function RBS n n N1 0 0 to 3 Sets the 2 bit immediate data n in the regist...

Page 316: ...han the TBR or TCALL instruction is referenced An instruction using taddr taddr 1 as its operation code is executed Remark Function in this section is applicable to the µPD750008 whose program counter consists of 13 bits addr 0000H to 1FFFH However this is also applicable to the µPD750004 whose program counter consists of 12 bits addr 0000H to 0FFFH the µPD750006 whose program counter consists of ...

Page 317: ... GETI instruction If the instruction immediately preceding a GETI instruction has the skip function the GETI instruction is skipped as with other 1 byte instructions If an instruction referenced with a GETI instruction has the skip function the instruction immediately following the GETI instruction is skipped If a GETI instruction references an instruction having a string effect the following proc...

Page 318: ...mple MOV HL 00H MOV XA FFH are replaced with GETI instructions CALL SUB1 BR SUB2 ORG 20H HL00 MOV HL 00H XAFF MOV XA FFH CSUB1 TCALL SUB1 BSUB2 TBR SUB2 GET HL00 MOV HL 00H GETI BSUB2 BR SUB2 GETI CSUB1 CALL SUB1 GETI XAFF MOV XA FFH ...

Page 319: ...ddr CALLF faddr 1 2 Instruction execution time Pin connection Stack Instruction µPD75008 µPD750008 µPD75P0016 P33 P30 122 µs when operating at 32 768 kHz One time PROM 0000H 3FFFH 16384 x 8 bits VPP P33 MD3 P30 MD0 Masked ROM 0000H 1FFFH 8192 x 8 bits 000H 1FFH 512 x 4 bits 75XL CPU equivalent to the 75X high end CPU 215 fX 217 fX select Fixed to 215 fX able by a mask option 0 95 1 91 3 81 15 3 µs...

Page 320: ...4 32 kHz when the main system clock operates at 4 19 MHz 2 86 5 72 45 8 kHz when the main system clock operates at 6 0 MHz 3 channels Basic interval timer 1 Timer event counter 1 Clock timer 1 F 524 262 65 5 kHz when the main system clock operates at 4 19 MHz 2 kHz 3 modes supported Three wire serial I O mode First transferred bit switchable between the LSB and MSB Two wire serial I O mode SBI mod...

Page 321: ...ce file are guaranteed only on the above host machines and OSs RA75X relocatable assembler Host machine PC 9800 series IBM PC AT and compatibles Distribution media 3 5 inch 2HD 5 25 inch 2HD 3 5 inch 2HC 5 25 inch 2HC Part number µS5A13RA75X µS5A10RA75X µS7B13RA75X µS7B10RA75X OS MS DOS Ver 3 30 to Ver 6 2Note See OS for IBM PC Device file Host machine PC 9800 series IBM PC AT and compatibles Dist...

Page 322: ...rt number µS5A13PG1500 µS5A10PG1500 µS7B13PG1500 µS7B10PG1500 The PG 1500 PROM programmer is used together with an accessory board and optional program adapter It allows the user to program a single chip microcomputer containing PROM from a standalone terminal or a host machine The PG 1500 can be used to program typical 256K bit to 4M bit PROMs The PA 75P008CU is a PROM programmer adapter provided...

Page 323: ...emulator together with optional emulation board IE 75300 R EM and emulation probe For efficient debugging connect the emulator to the host machine and a PROM programmer The IE 75300 R EM is an emulation board used to evaluate an application system using the µPD750008 subseries Use this board together with the IE 75000 R or IE 75001 R The EP 75008GB R is an emulation probe for the µPD75008GB and µP...

Page 324: ... Version PC DOS Ver 3 1 to Ver 6 3 J6 1 VNote to J6 3 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 VNote to J6 2 VNote IBM DOSTM J5 02 VNote Note Only English version is supported Caution These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or later ...

Page 325: ...ntaining PROM µPD75P0016CU PROM programmer PG 1500 Programmer adapter PA 75P008CU RS 232 C Centronics interface IE control program PG 1500 controller Host machine PC 9800 series IBM PC AT Symbolic debugging is possible µPD75P0016GB The in circuit emulators do not contain the IE 75300 R EM to be ordered EV 9200G 44 Development Tool Configuration Device file Notes 1 2 Relocatable assembler ...

Page 326: ...306 µPD750008 USER S MANUAL Drawings of the Conversion Socket EV 9200G 44 and Recommended Pattern on Boards Figure B 1 Drawings of the EV 9200G 44 Reference EV 9200G 44 G0 ...

Page 327: ...ards for the EV 9200G 44 Reference EV 9200G 44 P0 Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL IEI 1207 ...

Page 328: ...308 µPD750008 USER S MANUAL MEMO ...

Page 329: ...a for ordering Use three UV EPROMs having the same contents or 3 5 or 5 25 inch IBM format floppy disk in ordering a masked ROM Prepare a mask option information sheet describing the mask option data 3 Preparation of the required documents Prepare the following documents when ordering a masked ROM Masked ROM order sheet Masked ROM order check sheet Mask option information sheet 4 Ordering Send a s...

Page 330: ...310 µPD750008 USER S MANUAL MEMO ...

Page 331: ...A mem 245 269 XCH XA mem 245 269 XCH A reg1 245 269 XCH XA rp 245 269 Table reference instructions MOVT XA PCDE 246 270 MOVT XA PCXA 246 271 MOVT XA BCDE 246 272 MOVT XA BCXA 246 272 Bit transfer instructions MOV1 CY fmem bit 246 273 MOV1 CY pmem L 246 273 MOV1 CY H mem bit 246 273 MOV1 fmem bit CY 246 273 MOV1 pmem L CY 246 273 MOV1 H mem bit CY 246 273 Arithmetic logical instructions ADDS A n4 2...

Page 332: ... instructions SET1 mem bit 248 282 SET1 fmem bit 248 282 SET1 pmem L 248 282 SET1 H mem bit 248 282 CLR1 mem bit 248 282 CLR1 fmem bit 248 282 CLR1 pmem L 248 282 CLR1 H mem bit 248 282 SKT mem bit 248 283 SKT fmem bit 248 283 SKT pmem L 248 283 SKT H mem bit 248 283 SKF mem bit 248 283 SKF fmem bit 248 283 SKF pmem L 248 283 SKF H mem bit 248 283 SKTCLR fmem bit 248 283 SKTCLR pmem L 248 283 SKTC...

Page 333: ...2 PUSH rp 255 292 PUSH BS 255 293 POP rp 255 293 POP BS 255 293 Interrupt control instructions EI 255 293 EI IExxx 255 293 DI 255 293 DI IExxx 255 294 I O instructions IN A PORTn 255 294 IN XA PORTn 255 294 OUT PORTn A 255 294 OUT PORTn XA 255 294 CPU control instructions HALT 255 295 STOP 255 295 NOP 255 295 Special instructions SEL RBn 256 295 SEL MBn 256 295 GETI taddr 256 296 APPENDIX D INSTRU...

Page 334: ...251 288 BR PCDE 250 287 BR PCXA 250 287 BR addr 250 285 BR addr 250 285 BR addr1 250 285 BRA addr1 251 285 BRCB caddr 251 286 C CALL addr 252 289 CALLA addr1 251 289 CALLF faddr 252 290 CLR1 CY 247 281 CLR1 fmem bit 248 282 CLR1 mem bit 248 282 CLR1 pmem L 248 282 CLR1 H mem bit 248 282 D DECS reg 247 280 DECS rp 247 280 DI 255 293 DI IExxx 255 294 E EI 255 293 EI IExxx 255 293 G GETI taddr 256 29...

Page 335: ...OT1 CY 247 282 O OR A n4 247 277 OR A HL 247 277 OR rp 1 XA 247 278 OR XA rp 247 277 OR1 CY fmem bit 248 284 OR1 CY pmem L 248 284 OR1 CY H mem bit 248 284 OUT PORTn A 255 294 OUT PORTn XA 255 294 P POP BS 255 293 POP rp 255 293 PUSH BS 255 293 PUSH rp 255 292 R RET 253 291 RETI 254 292 RETS 254 291 RORC A 247 279 S SEL MBn 256 295 SEL RBn 256 295 SET1 CY 247 281 SET1 fmem bit 248 282 SET1 mem bit...

Page 336: ...276 SUBS A HL 246 275 SUBS rp 1 XA 246 276 SUBS XA rp 246 275 T TBR addr 256 288 TCALL addr 256 290 X XCH A mem 245 269 XCH A reg1 245 269 XCH A HL 245 268 XCH A HL 245 268 XCH A HL 245 268 XCH A rpa1 245 268 XCH XA mem 245 269 XCH XA rp 245 269 XCH XA HL 245 269 XOR A n4 247 278 XOR A HL 247 278 XOR rp 1 XA 247 278 XOR XA rp 247 278 XOR1 CY fmem bit 248 284 XOR1 CY pmem L 248 284 XOR1 CY H mem bi...

Page 337: ...rrupt master enable flag 189 Interrupt request flag for clock timer 210 Interrupt status flag 63 194 INT0 edge detection mode register 193 INT0 interrupt enable flag 187 INT0 interrupt request flag 187 INT1 edge detection mode register 193 INT1 interrupt enable flag 187 INT1 interrupt request flag 187 INT2 edge detection mode register 213 INT2 interrupt enable flag 210 INT2 interrupt request flag ...

Page 338: ... Skip flag 63 Slave address register 134 Stack bank select register 46 58 Stack pointer 58 Sub oscillator control register 93 System clock control register 88 T Timer counter 1 interrupt enable flag 187 Timer counter 1 interrupt request flag 187 Timer counter 1 mode register 111 Timer counter 1 modulo register 110 Timer counter 1 output enable flag 114 Timer counter count 1 register 110 Timer even...

Page 339: ...33 COI 128 CSIE 128 CSIM 127 CY 62 I IE0 187 IE1 187 IE2 210 IE4 187 IEBT 187 IECSI 187 IET0 187 IET1 187 IEW 210 IM0 IM1 193 IM2 213 IME 189 IRQ0 187 IRQ1 187 IRQ2 210 IRQ4 187 IRQBT 187 IRQCSI 187 IRQT0 187 IRQT1 187 IRQW 210 IST0 63 194 IST1 63 194 K KR0 KR7 211 M MBE 21 64 MBS 21 65 P PC 47 PCC 86 PMGA 75 PMGB 75 PMGC 75 POGA 82 POGB 82 PORT0 PORT8 68 PSW 62 R RBE 34 64 RBS 34 65 RELD 133 RELT...

Page 340: ...320 µPD750008 USER S MANUAL S SBIC 131 SBS 46 58 SCC 88 SIO 134 SK0 SK1 SK2 63 SOS 93 SP 58 SVA 134 T T0 109 T1 110 TOE0 114 TOE1 114 TM0 112 TM1 113 TMOD0 109 TMOD1 110 W WDTM 101 WM 106 WUP 128 ...

Page 341: ... description for the mask option when using the feedback resistor Chapter 5 was added in the section Sub oscillator control register The description for the interrupt enable flag was added in Section 6 3 Chapter 6 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS Table 6 4 Identifying Interrupt Sharing Vector Table Address was added in Section 6 6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS The...

Page 342: ...322 µPD750008 USER S MANUAL MEMO ...

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NEC PD750004, User Manual, Page: 10 / 342

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