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1.6.10
Clamp pulse
The clamp pulse signal CLP is output from pin 22 of the MPU IC101 with the polarity POSI.
When "2" is selected in the OSD adjustment item "EDGE LOCK", the signal is triggered at the
front edge of HSYNC, and when "1" is selected, the signal is triggered at the rear edge.
1.6.11
SPARK
If it is electrically discharged in the CRT tube, the GND level of the high-voltage system circuit
is considerably varied. GND of this high-voltage system is connected to the MPU IC101 pin 25
via C103. The voltage level of MPU IC101 pin 25 is normally set at HI. If GND in the high-
voltage system varies since it is electrically discharged in the CRT tube, the current will flow to
R130 to set MPU IC101 pin 25 at the LO level. Pin 25 is the external interrupt terminal that
detects the trailing edge. When the trailing edge is detected, the MPU forcibly applies S/W
RESET. (It is the same as when the power SW is turned ON.)
The above operation prevents the monitor from going out of control when it is electrically dis-
charged in the CRT tube.
1.6.12
Avoidance operation during input SYNC switching
The horizontal LOCK output signal of the deflection processor IC601 pin 46 is connected to the
MPU IC101 pin 23. MPU IC101 pin 23 is the external interrupt terminal of the trailing edge
detection. Though the voltage level of the LOCK signal is normally set at HI, IC601 outputs LO
when the horizontal deflection lock is released since the input SYNC is switched.
When the MPU detects the trailing edge, the HSK signal of IC101 pin 50 is set at HI, and the
simulative SYNC that is near the original frequency is output from pin 26 and pin 27. HSK
signal is used to set +B, voltage at MIN.
This reduces the stress when the input SYNC is switched for a short time.
1.6.13
CS switch and vertical linearity switch
Microcomputer IC101 outputs CS switch signal and vertical linearity switch signal via I/O ex-
pander IC102, and corrects the linearity in the screen.
Patterns of vertical linearity switch are shown in the table below.
As for CS switch pattern, refer to Table 4.
1.6.14
H/W RESET
The +5V power is connected to pin 2 of the voltage detector IC100, and IC100 pin 1 output is
connected to the MPU IC101 pin 54.
On the voltage detector, pin 1 is the open drain output, being turned OFF when pin 2 voltage is
4.5V or more, and ON when it is 4.5V or less. When the power switch is turned ON, IC100 pin
1 is turned ON and the MPU pin 54 level is set at 0V since +5V has not started up.
When the voltage of IC100 pin 2 becomes 4.5V or more, IC100 pin 1 will be turned OFF, and
the voltage of the MPU pin 54 rises with the time constants of R100 and C100.
When the voltage of the MPU pin 54 becomes 3.5V or more, the MPU will start operating.
Table 8 SW_VLIN1, SW_VLIN2 select pattern (IC102)
Vertical frequency
50Hz
`
77.9Hz
78Hz
`
89.9Hz
90Hz
`
124.9Hz
125Hz
`
160Hz
SW-VLIN1
Pin 12
LO
HI
LO
HI
SW-VLIN2
Pin 13
LO
LO
HI
HI
Summary of Contents for MultiSync FP1355 FP1355 FP1355
Page 23: ...1 17 Q502 Q502 Damper diode Current waveform fh 106k ...
Page 25: ...1 19 Q502 Q502 Damper diode Current waveform Q502 Ic Q502 Vce ...
Page 58: ...1 52 Figure 25 IC211 MC13289ASP block diagram ...
Page 63: ...1 57 Figure 30 IC212 XC3824P2 block diagram ...
Page 65: ...1 59 1 11 Wave form of main circuit voltage ...
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Page 120: ...MultiSync FP1355 User s Manual ...
Page 144: ... VSP C0464 REVISE 2 ...
Page 166: ...Fig 2 BEZEL LOGO VSP C0464 COLOR OF LETTERING Kingfisher Blue 6704 11 5 24 5 66 ...
Page 169: ...VSP C0464 Fig 5 1 PRINTING SPECIFICATION OF CARTON BOX North America ...
Page 170: ...VSP C0464 Fig 5 2 PRINTING SPECIFICATION OF CARTON BOX Europe ...
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