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CHAPTER 2 PCI INTERFACE

Information S14769EJ1V0IF00

15

Q.2.12

How long does it take for the EEPROM™ connection check and automatic loading?

A.2.12

The connection check takes about 600 clocks (BUSCLK input) and automatic loading about 2400 clocks (BUSCLK

input).

Reference:

µ

PD98409 User’s Manual 4.2 Serial EEPROM Interface

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Summary of Contents for mPD98409

Page 1: ...Document No S14769EJ1V0IFJ1 1st edition Date Published December 2000 N CP K Printed in Japan Information PD98409 Q A NEASCOT S40CTM ATM LIGHT SAR CONTROLLER 2000...

Page 2: ...Information S14769EJ1V0IF00 2 MEMO...

Page 3: ...connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing...

Page 4: ...ility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must in...

Page 5: ...al Refer to the table of contents for the item that is unclear Readers of this manual are required to have general knowledge in the fields of electricity logic circuits and microcontrollers When desig...

Page 6: ...Information S14769EJ1V0IF00 6 MEMO...

Page 7: ...2 How long does it take for the EEPROM connection check and automatic loading 15 CHAPTER 3 UTOPIA INTERFACE 16 Q 3 1 When should the TCLAV signal be deasserted 16 Q 3 2 What is the phase difference de...

Page 8: ...et be added during transmission when the transmit VC is active 24 Q 7 6 When are the contents of packet descriptor Word0 stored in transmit VC table Word0 25 Q 7 7 Is there a limit to the number of VC...

Page 9: ...ceive indication issued even when a Raw cell is received 34 CHAPTER 10 COMMANDS 35 Q 10 1 What will happen if the Tx_Ready command is issued to a VC that is transmitting a packet active VC 35 Q 10 2 W...

Page 10: ...nterface At that time does the handling of the VDD5 pin influence this connection 40 CHAPTER 15 OTHER ITEMS 41 Q 15 1 Access is prohibited for 20 clocks BUSCLK input after reset Does this mean that ac...

Page 11: ...does the RSTOUT_B pin operate A 1 1 The RSTOUT_B pin goes low at the same time as the RST_B pin and holds the low level for 11 to 22 clocks BUSCLK input after the RST_B pin has gone high Reference PD9...

Page 12: ...User s Manual Regarding read commands however the command issued differs depending on the Cache line size setting When the Cache line size is set to 4 8 or 16 the commands shown in 4 1 3 2 a Read tran...

Page 13: ...if an invalid command is received A 2 5 The PD98409 does not respond to the transfer DEVSEL_B does not become active Reference PD98409 User s Manual 4 1 3 1 Slave transaction Q 2 6 Are the registers...

Page 14: ...Configuration register Q 2 10 Why is it impossible to write 0 to Status bits 31 to 27 and 24 in the PCI configuration register A 2 10 Write operations to the Status register conform to the PCI standa...

Page 15: ...2 12 How long does it take for the EEPROM connection check and automatic loading A 2 12 The connection check takes about 600 clocks BUSCLK input and automatic loading about 2400 clocks BUSCLK input Re...

Page 16: ...53 52 51 50 5 4 3 2 1 H2 P45 P44 X X H1 X X P48 P47 P46 Reference PD98409 User s Manual 4 3 1 1 Transmit interface Q 3 2 What is the phase difference delay between TCLK and RCLK A 3 2 The phase differ...

Page 17: ...ls of the operation refer to 4 3 1 UTOPIA interface in the PD98409 User s Manual Reference PD98409 User s Manual 4 3 1 2 Receive interface Q 3 6 What is the status of the Tx7 to Tx0 pins while the TEN...

Page 18: ...ol Memory Q 4 2 How long does it take for the control memory to be automatically initialized after reset A 4 2 It takes about 1024 clocks BUSCLK input Reference PD98409 User s Manual 5 1 2 Initializin...

Page 19: ...10000h OK NG XXX20000h XXX20000h 64 KB boundary 64 KB boundary System memory System memory XXX10000h 64 KB boundary 64 KB boundary Reference PD98409 User s Manual 5 3 1 Setting of mailbox Q 5 2 When d...

Page 20: ...Line speed P 1 Here is an example of a setting where the line speed is 155 52 Mbps Example Line speed 155 52 Mbps Average rate 38 88 Mbps Peak rate 51 84 Mbps I M 38 88 155 52 1 4 P 155 52 51 84 1 2 R...

Page 21: ...haper 0 I M 2 3 P 0 C 2 VC1 VC2 VC3 VC1 VC2 VC3 UN UN UN UN UN UN UN UN UN UN UN UN Example of cell transmission VC1 VC2 and VC3 use shaper 1 Setting of shaper 1 I M 1 9 P 0 C 2 Normal cell transmissi...

Page 22: ...e cell data is executed If the transmit FIFO has become full the DMA operation to read cell data is stopped Reference PD98409 User s Manual 5 4 4 7 Algorithm operation Q 6 7 Does the host CPU have to...

Page 23: ...data is resumed Reference PD98409 User s Manual 5 4 5 Transmit operation Q 7 2 Is there a limit to the size of the transmit queue of each VC configured with a transmit packet descriptor A 7 2 No Refer...

Page 24: ...this case issue an additional Tx_Ready command to the position of the blank packet descriptor Tx queue read pointer on completion of transmission Transmit queue Link pointer Blank PD Valid PD A new p...

Page 25: ...sed to one shaper Reference PD98409 User s Manual 5 4 3 Transmit channel transmit VC Q 7 8 Is there any problem if the value of the vacant field Word1 Word2 bits 31 to 16 of the transmit packet descri...

Page 26: ...values on the system memory are not rewritten 0 16 15 0 31 0 ADDRESS SIZE 30 31 LAST Reference PD98409 User s Manual 5 4 2 Structure of transmit data Q 7 10 What does the Packet queue pointer field f...

Page 27: ...epending on the setting of the shaper to which each VC is linked 2 Use one transmit VC and the packet descriptor of its transmit queue for an AAL 5 packet and for an OAM F5 cell In this case the AAL 5...

Page 28: ...2 How is a CRC 10 error reported when a Raw cell is received Is it possible to disable error checking A 8 2 A CRC 10 error is reported by the CE bit in the Raw cell data when a Raw cell is received At...

Page 29: ...batch is consumed even if a receive indication that includes error information has been reported A 8 5 Yes The batches consumed until the error occurs can be recognized from the Packet size and Packe...

Page 30: ...User s Manual 5 5 5 2 Storing receive data Q 8 9 Pools 0 to 7 are allocated as the receive pools for Raw cells Can all the pools from 0 to 7 be used for receiving Raw cells or can only one of the pool...

Page 31: ...er bits VPI lower bits VCI higher bits VCI lower bits VPI higher bits VPI lower bits SHIFT 4 bits VCI lower bits VPI 8 bits VCI 16 bits Area that is invalidated by MASK when MASK 00FFh Area invalidate...

Page 32: ...receive packet The packet size can be specified to be in cell units or byte units If an error occurs however the receive indication always reports the Packet size field in cell units At this time the...

Page 33: ...orted for VPI VCI A 9 2 The transmission side can set and transmit any 24 bit VPI VCI value The reception side reduces the 24 bit VPI VCI value to 15 bits This reduction is done as follows VPI is shif...

Page 34: ...tion Q 9 4 Is the receive indication issued even when a Raw cell is received A 9 4 The receive indication is not issued when a Raw cell is received When a Raw cell is received it is stored in the rece...

Page 35: ...nd is issued with an incorrect setting for the transmit or receive VC specified by the R T bit of the command A 10 2 The PD98409 may malfunction if the setting of the R T bit is incorrect because it p...

Page 36: ...two times to close a receive VC after the receive look up table has been disabled in the following sequence 1 Disable the receive look up table 2 Issue the NOP command two times 3 Issue the receive De...

Page 37: ...ng the data PD98409 Host CPU UTOPIA Loopback Reference PD98409 User s Manual 5 8 Loopback Function Q 11 2 Does the pin status of the UTOPIA interface affect the transmit receive operations of the PD98...

Page 38: ...09 User s Manual 7 2 11 ECCR 7 2 12 ERDR Q 12 3 Can transmission reception be temporarily halted by clearing the SE and RE bits of the GMR register during transmission reception A 12 3 Yes If the SE a...

Page 39: ...pins while the JRST_B pin is pulled up Input the clock five times to the JCK pin while the JMS pin is pulled up When the JRST_B pin is used The JTAG function can be reset by inputting a low level to...

Page 40: ...nsumption is calculated as the normal current consumption refer to the PD98409 Data Sheet 3 3 V Reference PD98409 Data Sheet 2 Electrical Specifications Q 14 2 Can a 5 V device be directly connected t...

Page 41: ...Manual 5 1 Initialization Q 15 2 Are there any differences in the initialization of the device between a hardware reset input of a low level to the RST_B pin and a software reset writing the SWR regi...

Page 42: ...Information S14769EJ1V0IF00 42 MEMO...

Page 43: ...02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 2...

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