CHAPTER 8 RECEPTION
Information S14769EJ1V0IF00
30
Q.8.7
How should the T1 time register (T1R) be set to detect a T1 error?
A.8.7
The setting of the T1R register should be the system clock time (BUSCLK input)
×
64K. For example, where T1R
= 5, the time required to detect a T1 error is 320K clocks (about 9.8 ms where BUSCLK = 33 MHz).
Reference:
µ
PD98409 User’s Manual 5.5.5 (3) T1 timer (reassembly timer)
Q.8.8
Can the receive pool for Raw cells be shared with the receive pool for AAL-5?
A.8.8
No. Separately set the receive pools for Raw cells and AAL-5.
Reference:
µ
PD98409 User’s Manual 5.5.5 (2) Storing receive data
Q.8.9
Pools 0 to 7 are allocated as the receive pools for Raw cells. Can all the pools from 0 to 7 be used for receiving
Raw cells, or can only one of the pools from 0 to 7 be used?
A.8.9
All the pools from 0 to 7 can be used for receiving Raw cells.
Reference:
µ
PD98409 User’s Manual 5.5.2 (3) Pool storing raw cell
Q.8.10
What is the Alert level of a receive pool descriptor? Are the settings and interrupts of the Alert level valid for a
Raw cell pool?
A.8.10
The settings and interrupts of the Alert level are only valid for the AAL-5 pool. This function is invalid for the Raw
cell pool, and in the
µ
PD98409, values set in the Alert level field are ignored.
Reference:
µ
PD98409 User’s Manual 5.5.2 (3) Pool storing raw cell
